The HP interface is a high-speed interface, used for the interface between memory or chip and chip, HR can accept a wide level standard.
The 7 series FPGAs offer both high-performance(HP) and high-range(HR)I/O banks. The HP I/O banks are designed to meet the performance requirements of high-speed memory and other chip-to-chip interfaces with voltages up to 1.8V. The HR I/O banks are designed to support a wider range of I/O standards with voltages up to 3.3V. Table 1-1 highlights the features supported in the HP and HR I/O banks. Refer to Table 1-1 for help when making initial decisions on I/O banks for a particular design's requirements. See the specific device family data sheet for details on the performance and other electrical requirements of the HP and HR I/O banks.
HP interface is a high-speed interface, used for memory or chip-to-chip interface, HR can accept a wide range of level standards.
Notes:
1. Not all I/O standards and drive strengths are supported in both the HP and HR I/O banks. The I/O Bank Availability column in Table 1-55 shows the specific I/O standards that are available in the HP and HR I/O banks.
2. Although LVDS is generally considered a 2.5V I/O standard, it is supported in both the HR and HP I/O banks.
FPGA Spartan-3A Family 700K Gates 13248 Cells 770MHz 90nm Technology 1.2V 400-Pin FBGA
FPGA Spartan-3AN Family 700K Gates 13248 Cells 770MHz 90nm Technology 1.2V Automotive Medical 484-Pin FBGA
FPGA Spartan-3A DSP Family 1.8M Gates 37440 Cells 667MHz 90nm Technology 1.2V 484-Pin CSBGA
FPGA Spartan-3A DSP Family 1.8M Gates 37440 Cells 770MHz 90nm Technology 1.2V 676-Pin FBGA
FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
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