The layout is to assign physical locations to units, macro modules, etc. on the layout, so that the units, macro modules, etc. do not overlap each other. The allocation needs to optimize the cost function according to the specific constraints given by the user. After the layout, the exact locations of the cells and pins have been determined, and the required interconnections have also been determined. The area reserved for wiring is called the wiring area. The wiring must be carried out in the wiring area, and the wiring rules must be followed, and the wiring rules must not be violated.
Layout is a design step that determines the location of the circuit unit such as the core unit and macro module on the layout plane. Given a set of standard cells and macro modules, and the characteristic width and height of these components, a set of wires connecting these cells, macro modules and pins is given. The wiring process is used to realize the connection of each module, and to generate the geometric interconnection layout of all the connections. It is necessary to add appropriate constraint information, such as timing. Different designs may have different target requirements for the routing process. Generally, the design will require the minimum total length of the routing. The timing-driven design also requires that all connections can meet the timing constraints.
During layout, a specific optimization objective function needs to be optimized. The objective function usually includes the wire length, congestion, the number of cutting lines and chip performance. Since some goals, such as wire length, cannot be accurately obtained before detailed wiring, this kind of goal optimization needs to be estimated during the layout process.
During layout, a specific optimization objective function needs to be optimized. The objective function usually includes the wire length, congestion, the number of cutting lines and chip performance. Since some goals, such as wire length, cannot be accurately obtained before detailed wiring, this kind of goal optimization needs to be estimated during the layout process.
Layout tools mainly use two types of layout algorithms, heuristic layout and incremental iterative layout. Heuristic layout uses a series of rules to achieve, commonly used methods are min-cut algorithm and eigenvalue algorithm. When dividing the system, the layout usually starts with a heuristic scheme, followed by an incremental algorithm.
The Min-cut layout method is implemented using a series of continuous divisions.First, the layout area is divided into two parts, then the logical units on both sides are exchanged to minimize the number of cut lines, and the above process is repeated until all logical units are completed. layout. The incremental iteration method attempts to improve the quality of the layout by moving logical units for an existing layout. The algorithm mainly consists of two parts, selection rules to decide which logical units to try to move to evaluate the rules to determine whether to move the selected logical unit.
The methods used for wiring can be divided into two categories.The first one uses a two-stage solution to solve the wiring problem.First, global wiring is performed to produce a loose wiring result, and then the detailed wiring surface is mapped to map each wiring to The final geometric layout. The second method is called regional wiring. This method attempts to solve all wiring problems at once. For a wiring, all wiring areas need to be considered, and the calculation is very huge.
Global wiring does not make actual wiring, but only plans for interconnection, seeks a wiring path for each wire network, allocates each part of each wire network to each wiring channel reasonably, and clearly defines each wiring channel area The problem of wiring is to provide detailed wiring guidance for detailed wiring. Global routing consists of three stages, area definition, area assignment, and pin assignment.
Detailed wiring includes channel wiring, 2D-switchbox and 3D-switchbox wiring. The detailed wiring uses the channel information obtained by the global wiring to determine the exact location and metal layer of each interconnect. Wiring rules should be observed during the wiring process, such as the distance between the through holes and the distance between the through holes and the metal wires. Usually in the multi-layer process, each metal wiring layer is routed in only one direction to reduce the crossing of wires. After the detailed wiring completes the interconnection of each logic unit, it mainly performs the optimization work of the completed wiring, which mainly includes minimizing the length and area of the interconnection, reducing the number of vias between layers, and minimizing the critical path delay.
After the detailed wiring is completed, the exact geometric information of the connection can be extracted and used to calculate the delay model of the connection, not only to consider the geometric length and width of the connection, the distribution of the wiring layer and the through hole, but also to consider the connection and the Other connections. It may be necessary to iterate the process if some contacts cannot reach their timing constraints.
FPGA Spartan-3A Family 700K Gates 13248 Cells 770MHz 90nm Technology 1.2V 484-Pin FBGA
FPGA Spartan-3AN Family 700K Gates 13248 Cells 667MHz 90nm Technology 1.2V Automotive Medical 484-Pin FBGA
Spartan and Spartan-XL Families Field Programmable Gate Arrays
FPGA Spartan-3A DSP Family 1.8M Gates 37440 Cells 770MHz 90nm Technology 1.2V 484-Pin LCSBGA
FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
Support
