VCCAUX_IO

Introduction

The auxiliary I/O (VCCAUX_IO) supply rail is only present in HP I/O banks and provides power to the I/O circuitry. The Kintex-7 and Virtex-7 FPGAs data sheets contain a table titled Maximum Physical Interface (PHY) Rate for Memory Interfaces that references VCCAUX_IO. This table indicates how the VCCAUX_IO pins can be powered at either 1.8V (default), or optionally at 2.0V to achieve higher frequency performance for certain types of memory interfaces. Although this table is designed for memory interfaces, it can also provide guidance on powering VCCAUX_IO for other high-speed single-ended interfaces based on the target bit rates. The table does not apply to LVDS, which uses a different type of driver circuit than the single-ended drivers that are more affected by the VCCAUX_IO level. Thus, for LVDS interfaces, it does not matter which voltage level the VCCAUX_IO rail is powered at. The default value of 1.8V affords a lower-power consumption and provides very close to the same performance in the I/Os. The 2.0V option is available when the slightly-increased performance is required for the very fastest bit rates supported for the single-ended drivers.

There is a design constraint for I/O nets and primitives called VCCAUX_IO, which should be specified in the design if the VCCAUX_IO pins for any banks are to be set at 2.0V. See 7 Series FPGA SelectIO Attributes/Constraints, page 46 for information on this constraint. The VCCAUX_IO pins are connected together internally inside Kintex-7 and Virtex-7 device packages in groups of three or four HP I/O banks. The package files chapter of UG475: 7 Series FPGA Packaging and Pinout Specification contains links to the ASCII package files, and the figures in the device diagrams chapter indicate which device/package combinations contain HP I/O banks with VCCAUX_IO pins. The ASCII package files indicate which bank’s VCCAUX_IO pins are grouped together inside the package. The VCCAUX_IO package pin names have the syntax VCCAUX_IO_G#, where the # is the internal group number. The package files contain a column called “VCCAUX Group” that shows for every I/O pin which VCCAUX group that I/O bank is associated with. All I/O pins that are in the same VCCAUX_IO group must have VCCAUX_IO constraints on their nets or primitives that are compatible. All VCCAUX_IO pins that are grouped together should be tied to the same voltage rail on the board. FBG packages for Kintex-7 devices contain VCCAUX_IO pins but are no connects internally. All HP I/O banks in those packages are powered from the main VCCAUX rail instead.