It means that at any time, the output state is only determined by the combination of the input states at the same time, and has nothing to do with the previous state of the circuit, and has nothing to do with the state at other times.
FPGA Spartan-3A Family 700K Gates 13248 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
FPGA Spartan-3A Family 700K Gates 13248 Cells 770MHz 90nm Technology 1.2V 400-Pin FBGA
FPGA Virtex-II Family 1M Gates 11520 Cells 750MHz 0.15um Technology 1.5V 896-Pin FCBGA
FPGA Virtex-II Family 1M Gates 11520 Cells 820MHz 0.15um Technology 1.5V 896-Pin FCBGA
FPGA Spartan-3A Family 700K Gates 13248 Cells 770MHz 90nm Technology 1.2V 400-Pin FBGA
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