Libero Integrated Design Environment (IDE) is a complete software tool suite designed by Actel for all its FPGAs.
Libero Integrated Design Environment (IDE) is a complete software tool suite designed by Actel for all its FPGAs. Libero IDE can quickly and efficiently manage the entire design process, from design, synthesis and simulation, to basic planning, place and route, timing constraints and analysis, power analysis and program file generation. Libero's second-generation smart design tool, SmartDesign, provides an effective method for easily creating complete, system-on-chip (SoC) designs based on simple and complex processors. To learn more about SmartDesign, please visit the SmartDesign webpage (in English).
Libero IDE provides comprehensive power optimization and analysis tools for Actel's low-power Flash FPGA series products (including IGLOO, ProASIC3L and the latest member of the low-power FPGA series IGLOO PLUS).
Libero IDE provides the latest and best FPGA development tools from leading EDA vendors such as Mentor Graphics, SynaptiCAD and Synplicity. These tools, combined with the tools developed by Actel, allow users to quickly and easily manage Actel FPGA designs. Libero IDE has an intuitive user interface and a powerful design manager that can guide users through the design process, organize design files, and achieve seamless connection exchange between different development tools.
Powerful project and design process management A set of integrated design input tools and design methods: SmartDesign graphical SoC design generation function, which can automatically abstract HDL code kernel directory and configuration functions HDL and HDL template "user-defined components" generation function to achieve design Reuse ViewDraw schematic capture tool Actel provides a variety of cell libraries Synplify/Synplify Pro AE comprehensive tools to comprehensively optimize the performance and area utilization of Actel FPGA devices Synplify DSP AE in Simulink environment to achieve high-level DSP optimization test platform generation function, including through WaveFormer Lite AE achieves simulated stimulation. SynaptiCad's advanced analog excitation function ModelSim VHDL or Verilog code synthesis and post-layout behavior simulation function Designer tool provides physical design implementation, basic planning, physical constraints, and placement function timing and power-driven placement and routing for timing constraint management and analysis SmartTime environment SmartPower provides comprehensive power analysis for actual or "hypothetical" application scenarios. It has interfaces with FlashPro and Silicon Sculptor programming software. Identify AE debugging software designed for Actel flash memory. Silicon Explorer debugging software designed for Actel anti-fuse supports Windows and Linux operating system.
FPGA Spartan-3A Family 700K Gates 13248 Cells 667MHz 90nm Technology 1.2V 400-Pin FBGA
FPGA Spartan-3A Family 700K Gates 13248 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
FPGA Spartan-3A Family 700K Gates 13248 Cells 770MHz 90nm Technology 1.2V 400-Pin FBGA
FPGA Virtex-II Family 1M Gates 11520 Cells 750MHz 0.15um Technology 1.5V 896-Pin FCBGA
FPGA Virtex-II Family 1M Gates 11520 Cells 820MHz 0.15um Technology 1.5V 896-Pin FCBGA
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