This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > Wiki encyclopedia > SOPC


System-on-a-Programmable-Chip, you can program the system on chip. Using programmable logic technology to put the entire system on a piece of silicon, called SOPC. Programmable system on chip (SOPC) is a special embedded system: first, it is a system on chip (SOC), that is, a single chip completes the main logic functions of the entire system; second, it is a programmable system with a flexible design method It can be cut, expanded, and upgraded, and has the function of software and hardware programmable in the system.



English name: System On a Programmable Chip. SOPC experiment board Chinese translation: programmable system on chip

SOPC uses programmable logic technology to put the entire system on a silicon chip for embedded system research and electronic information processing. SOPC is a special embedded system, which is a system on chip (SOC), that is A single chip completes the main logic functions of the entire system, but it is not a simple SOC. It is also a programmable system with flexible design methods that can be cut, expanded, and upgraded, and has software and hardware programmable functions in the system.

Technical content

SOPC design technology covers the entire content of embedded system design technology, except for the software design technology centered on the processor and real-time multitasking operating system (RTOS), and the high-speed circuit design technology based on PCB and signal integrity analysis. SOPC also involves software and hardware co-design technologies that have attracted widespread attention. Because the main logic design of SOPC is carried out inside programmable logic devices, and BGA packaging has been widely used in the field of micro packaging, traditional debugging equipment, such as logic analyzers and digital oscilloscopes, has been difficult to perform direct test analysis. Therefore, higher requirements will be put forward for the software and hardware collaborative design technology based on simulation technology. At the same time, new debugging technologies have also emerged, such as Chip Scope ILA, Xilinx's on-chip logic analyzer, is an inexpensive real-time debugging tool on chip.


SOPC combines the advantages of SOC, PLD and FPGA, and generally has the following basic characteristics:

At least one embedded processor core is included;

With small capacity on-chip high-speed RAM resources;

Rich IP Core resources are available;

Sufficient on-chip programmable logic resources;

Processor debugging interface and FPGA programming interface;

May contain some programmable analog circuits;

Single chip, low power consumption, micro package.

Simple process

The complete SOPC system based on NiosII is a hardware and software system, so it can be divided into hardware and software during design. The hardware design of NiosII is to customize the appropriate CPU and peripherals, and is completed in SOPCBuider and QuartusII. Here you can flexibly customize many features and even instructions of NiosII CPU. You can use the large number of IP cores provided by Altera to speed up the development of NiosII peripherals and improve the performance of peripherals. You can also use third-party IP cores or VHDL to customize externally. Assume. After the hardware development of NiosII is completed, SOPCBuider can automatically generate the corresponding software development kit SDK corresponding to the customized NiosIICPU and peripheral system, memory, peripheral address mapping, etc., and enter the software development process based on the generated SDK. Users can use assembly or C, or even C++ for embedded programming, and use GNU tools or other third-party tools to compile, connect, and debug programs.

Step 1: Open the QuartusII software and click the tool button

Step 2: Click on the SOPCBuilder marked in red

Step 3: Customize the CPU

Step 4: Complete and download the nios circuit board

Development prospects

The programmable system-on-chip is the result of the integration of PLD and ASIC technologies. Currently, the manufacturing price of 0.13 micron ASIC products is still quite expensive. On the contrary, integrated hard or soft core CPU, DSP, memory, peripheral I/O and programmable logic can be used. System-on-chip programming has great advantages in application flexibility and price. Research, application status, level and development trends of programmable system-on-chip technology at home and abroad. Based on the analysis of the background, core technology and development direction of programmable system-on-chip technology, it is proposed that only when the interdisciplinary integration is realized can the programmable system-on-chip technology achieve a real leap and be widely used. Therefore, the programmable system on chip is called "the future of semiconductor industry".


Programmable system-on-chip technology mainly uses the following three directions:

1) Application based on FPGA embedded IP hard core. This programmable system-on-chip system refers to the pre-implantation of a processor in the FPGA. This allows the flexible hardware design of FPGA and the powerful software functions of the processor to be organically combined to efficiently implement a programmable system-on-chip system.

2) Application based on FPGA embedded IP soft core. This kind of programmable system-on-chip system refers to implanting a soft-core processor in FPGA, such as: NIOS II core and so on. Users can use corresponding EDA tools to construct NIOS II and its peripheral devices according to the design requirements, so that the embedded system can fully meet the requirements of user system design in terms of hardware structure, functional characteristics, and resource occupation.

3) Application based on HardCopy technology. This kind of programmable system-on-chip system refers to the direct conversion of a programmable system-on-chip system successfully implemented on an FPGA device to an ASIC through a specific technology. Combining the flexibility of large-capacity FPGAs with the market advantages of ASICs, it is possible to avoid the difficulty of directly designing ASICs for electronic products that require large quantities and are cost-sensitive.


  • XC2C256-6PQG208C


    CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 256MHz 0.18um Technology 1.8V 208-Pin PQFP

  • XC2C256-7CP132C


    CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 152MHz 0.18um Technology 1.8V 132-Pin CSBGA

  • XC2C256-7FTG256C


    CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 152MHz 0.18um Technology 1.8V 256-Pin FTBGA

  • XC3S400A-5FT256C


    FPGA Spartan-3A Family 400K Gates 8064 Cells 770MHz 90nm Technology 1.2V 256-Pin FTBGA

  • XC3S400AN-4FGG400I


    FPGA Spartan-3AN Family 400K Gates 8064 Cells 667MHz 90nm Technology 1.2V Medical 400-Pin FBGA

FPGA Tutorial Lattice FPGA
Need Help?


If you have any questions about the product and related issues, Please contact us.