XST

The meaning of XILINX XST comprehensive options

The so-called synthesis is to translate the design inputs such as HDL language and schematic into logical connections (netlists) of basic logic units such as AND, OR, NOT gates, RAM, and flip-flops, and optimize the optimization according to the goals and requirements (constraints) The generated logical connection generates an EDF file.

After input, simulation and pin assignment are completed, it can be synthesized and realized. Double-click Synthesize-XST in the process management area.

There may be 3 results of synthesis: if the synthesis is completely correct, there is a small green circle in front of Synthesize-XST; if there is a warning

Report, a small yellow circle with an exclamation mark appears, as shown in this example; if there is an error, a small red circle with a cross appears. Comprehensive

After completion, you can double-click View RTL Schematics to view the RTL-level structure diagram to see whether the integrated structure is implemented according to the design intent

Current circuit. ISE will automatically call the schematic editor ECS to browse the RTL structure. The resulting RTL structure is shown in the figure, and the comprehensive result is in line with the design

The intention of the person.

You can get icons for resource use.

Generally, when using XST, all attributes use default values. In fact, XST can provide rich and flexible attribute configuration for different logic designs.

The XST attributes embedded in ISE 13.2 are described below. Open the design project in ISE, select "Synthesis -XST" in the process management area and right-click, the pop-up interface is shown in the figure.

The XST configuration page is divided into three categories: Synthesis Options, HDL Language Options, and Xilinx Specific Options. They are used to set comprehensive global goals and overall strategies, HDL hardware syntax rules, and Xilinx unique structural properties.