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Xilinx netlist format. The text format specially produced by Xilinx.



The first statement is not something in the HDL language, but something in the synthesis tool.

The concept of synthesis is that you write Verilog code. But he is just code. In fact, it doesn't have any effect, just a behavior-level description of this module. But the computer cannot directly recognize verilog. Therefore, it must be translated through a compiler and synthesis tools. The compiler checks your syntax errors, as well as preliminary logic function checks. The synthesis tool then converts the corresponding design into a "netlist."

The actual circuit process to make your HDL code usable is as follows:

xilinx steps synphysize (comprehensive) translate (annotation), map (mapping), and place and route (place and route)

The steps of altera are complie (compilation) synphysize (synthesis) fitter (wiring)

The netlist file is generated after synthesis. This file is just the prototype of a circuit. After this step is completed, you can see the RTL (register transfer level) circuit. You can also see the technology circuit. The difference between the two will soon be understood when you see it. These two pictures are an intuitive display of the netlist. That is, the synthesizer finally synthesizes your logic circuit. Put it in the netlist file.

Note: When you reach the netlist layer, your HDL language is useless. At this time, you need to use the netlist file generated by the synthesizer to do the following steps. In other words, your language has been transformed into a circuit! ! ! The next step is to transplant the circuit to FPGA! ! ! ! !

After converting into a circuit: The following steps are to refine this netlist according to different FPGAs. For example, the tool can specifically calculate the delay of a certain signal. Including how much wiring delay and how much combinational logic delay. Then finally decide where to put this gate according to the internal structure of FPGA. This is place&route.

At this point, you have generated a real logic circuit, then what. Huhu~~ Generate a download file, and your FPGA or CPLD can run.


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