VITAL (VHDL Initiative Towards ASIC Libraries) VHDL model benchmark for ASIC, started by IEEE in 1992, launched VITAL2.1e version in December 1993, launched 2.2b version in March 1994, completed VITAL3.0 version in June 1995 , Or VITAL'95. Officially adopted as an international standard in September 1995, known as IEEE std 1076.4-1995.
The VITAL standard includes the following parts: timing package VITAL- Timing; basic component package VITAL-Primitives; introduction of delay mechanism; model establishment specification document. The timing package and basic components are placed together with Std-Logic-1164 package The technical characteristics of VITAL in the IEEE library are as follows.
(1) Flexible function designation: Provide a variety of basic components and provide a method to describe the truth table and state table. (2) Accurate time delay designation: The time delay can be described end-to-end and can be specified according to the different signal states Different delays. (3) Support accurate timing check function: provide check for setup time and hold time constraints (including negative timing constraint check), minimum pulse width and period check, and event conflict check function; or specify not to check. 4) Provide two-level model description specifications to facilitate implementation and optimization within the tool and improve simulation efficiency. (5) Based on existing industry standards: VHDL language IEEE std1076-1987 and std1076-1993; MVL standard 9-value logic system Std-Logic- 1164 (IEEE std1164-1993); Verilog's standard delay format OVI SDF v2.1.
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