Quartus II design is the most advanced and complex, used in the system-on-a-programmable-chip (SOPC) design environment. Quartus II design provides a comprehensive timing closure and LogicLock⢠block-based design flow. Quartus II design is the only software that includes programmable logic device (PLD) with timing closure and block-based design flow as its basic features. Quartus II design software improves performance, enhances functionality, and solves potential design delays. It is the first in the industrial field to provide a unified workflow for FPGA and mask-programmed devices development.
As a programmable logic design environment, Altera Quartus II is more and more popular with digital system designers due to its powerful design capabilities and intuitive and easy-to-use interface. The latest version currently available for official download is v17.0.
Altera Quartus II (3.0 and higher) design software is the industry's only design tool that provides a unified design flow for FPGAs and fixed-function HardCopy devices. Engineers use the same low-cost tools for functional verification and prototyping of Stratix FPGAs, and can design HardCopy Stratix devices for mass production. System designers can now use the Quartus II software to evaluate the performance and power consumption of HardCopy Stratix devices and design the maximum throughput accordingly.
Altera's Quartus II programmable logic software belongs to the fourth-generation PLD development platform. The platform supports design requirements in a workgroup environment, including support for Internet-based collaborative design. The Quartus platform is compatible with development tools from EDA vendors such as Cadence, ExemplarLogic, MentorGraphics, Synopsys, and Synplicity. The software's LogicLock module design function has been improved, FastFit compilation options have been added, network editing performance has been promoted, and debugging capabilities have been improved.
Version 2.0 Quartus II design software now supports Altera's APEX 20KE, APEX 20KC, APEX II, ARM's Excalibur embedded processor solution, Mercury, FLEX10KE and ACEX1K, and also supports MAX3000A, MAX7000 series product term devices. Designers of the MAX3000A and MAX7000 can now use all the powerful features only available in the QuartusII design software.
The QuartusII2.0 installation software is 290M, and the full installation is 700M. If you customize the installation and do not choose Excalibur embedded processor, the space required for installation is 460M, which is more than half the space requirement compared with QuartusII1.1 version, but it can support all ALTERA chips. Development. At the same time, the loading, compilation, and simulation speed of the software is much faster than that of version 1.1.
QuartusII2.0 design software improves the performance by an average of 15% by enhancing the hierarchical LogicLock module-level design. The LogicLock design process puts the placement of the entire module under the designer's control, and if necessary, an auxiliary layout can be used. The LogicLock design process allows designers to optimize and lock the performance of each module individually, while maintaining the performance of the entire system during the construction of large SOPC designs. The Quartus II design software version 2.0 integrates the new LogicLock design flow algorithm into future Altera devices. This algorithm takes full advantage of module-level design.
QuartusII2.0 adds a new quick adaptation compilation option. Selecting this option will shorten the compilation time by 50% compared to the default setting. The quick adaptation function retains the best performance settings and speeds up the compilation process. In this way, the layout adaptation algorithm has fewer iterations, faster compilation speed, and minimal impact on design performance.
Version 2.0 Quartus II design software introduces new features to speed up the verification process, which is usually the longest phase of the SOPC design process. During the initial compilation time, the new SignalProbe technology allows users to route internal nodes to unused pins for analysis while preserving the original wiring, time limit, and design files of the design. SignalProbe technology completes the function of existing SignalTap embedded logic analysis. Moreover, designers can use the HDL test templates provided in the new version to quickly develop HDL simulation vectors.
Version 2.0 of the Quartus II design software can also automatically create a complete HDL test platform from the Quartus II simulator waveform file.
Version 2.0 Quartus II design software also supports high-speed I/O design, and generates a dedicated I/O buffer information specification (IBIS) model to import into commonly used EDA signal integration tools. The IBIS model is customized according to the I/O standard settings of each pin in the design, simplifying the analysis of third-party tools.
Version 5.0 or later supports dual-core CPU embedding.
Each new version of Altera will shorten its compilation speed. Because its compilation speed is really slow.
The kernel refers to the soft core (which can be customized by users according to their needs) can be implemented with NIOS II.
FPGA Spartan-3A Family 400K Gates 8064 Cells 770MHz 90nm Technology 1.2V 320-Pin FBGA
CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 256MHz 0.18um Technology 1.8V 144-Pin TQFP
CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 152MHz 0.18um Technology 1.8V 132-Pin CSBGA
FPGA Spartan-3A Family 400K Gates 8064 Cells 770MHz 90nm Technology 1.2V 320-Pin FBGA
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