Timing constraints are used by designers to pass a design's design performance goals to Xilinx implementation tools. Xilinx implementation tools are timing-driven, so during implementation, the implementation tools attempt to place and route logic to meet timing constraints.
FPGA Spartan-3A Family 50K Gates 1584 Cells 667MHz 90nm Technology 1.2V 144-Pin TQFP
FPGA Spartan-3A Family 50K Gates 1584 Cells 770MHz 90nm Technology 1.2V 256-Pin FTBGA
FPGA Spartan-3A Family 50K Gates 1584 Cells 770MHz 90nm Technology 1.2V 100-Pin VTQFP
FPGA XC5200 Family 23K Gates 1936 Cells 83MHz 0.5um Technology 5V 160-Pin PQFP
FPGA XC5200 Family 23K Gates 1936 Cells 83MHz 0.5um Technology 5V 304-Pin HPQFP
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