The startup block is used to control the internal reset during the configuration phase.Global write enable and global tri-state network The startup block is called STARTUP_VIRTEX in Virtex devices and STARTUP_VIRTEX2 in Virtex-II devices.
FPGA Spartan-3 Family 50K Gates 1728 Cells 725MHz 90nm Technology 1.2V 100-Pin VTQFP
FPGA Spartan-3A Family 50K Gates 1584 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
FPGA Spartan-3A Family 50K Gates 1584 Cells 667MHz 90nm Technology 1.2V 100-Pin VTQFP
FPGA Spartan-3A Family 50K Gates 1584 Cells 770MHz 90nm Technology 1.2V 100-Pin VTQFP
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Support
