The Stamp model is an industry standard format for board-level timing verification.
FPGA Spartan-3 Family 50K Gates 1728 Cells 725MHz 90nm Technology 1.2V 144-Pin TQFP EP
FPGA Spartan-3A Family 50K Gates 1584 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
FPGA Spartan-3A Family 50K Gates 1584 Cells 667MHz 90nm Technology 1.2V 144-Pin TQFP
FPGA Spartan-3A Family 50K Gates 1584 Cells 770MHz 90nm Technology 1.2V 144-Pin TQFP
Spartan and Spartan-XL Families Field Programmable Gate Arrays
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