CPLD (Complex Programmable Logic Device) is a device developed from PAL and GAL devices. It is relatively large in scale and complex in structure, and belongs to the scope of large-scale integrated circuits. It is a kind of digital integrated circuit that users construct logic functions according to their own needs. The basic design method is to use the integrated development software platform to generate corresponding target files with schematic diagrams, hardware description languages, etc., and transfer the code to the target chip through the download cable ("in-system" programming) to realize the designed digital system .
CPLD is mainly composed of programmable logic macro cells (MC, Macro Cell) around the center of the programmable interconnect matrix unit. Among them, the MC structure is more complicated, and has a complex I/O unit interconnection structure, and the user can generate a specific circuit structure according to needs to complete certain functions. Since the CPLD uses fixed-length metal wires to interconnect the logic blocks, the designed logic circuit has time predictability, avoiding the disadvantage of incomplete prediction of the timing of the segmented interconnect structure.
In the 1970s, the earliest programmable logic device, PLD, was born. The output structure is a programmable logic macro unit, because its hardware structure design can be completed by software (equivalent to manually designing the local indoor structure after the house is built), so its design has strong flexibility than pure hardware digital circuits , But their overly simple structure also makes them only able to implement smaller-scale circuits. In order to make up for the defect that PLD can only design small-scale circuits, in the mid-1980s, a complex programmable logic device, CPLD, was introduced. This application has penetrated into the network, instrumentation, automotive electronics, CNC machine tools, aerospace measurement and control equipment, etc.
It has the characteristics of flexible programming, high integration, short design and development cycle, wide application range, advanced development tools, low design and manufacturing costs, low hardware experience requirements for designers, standard products without testing, strong confidentiality, and popular prices. Large-scale circuit design can be realized, so it is widely used in product prototype design and product production (generally below 10,000 pieces). CPLD devices can be used in almost all applications where small and medium-sized general-purpose digital integrated circuits are used. CPLD devices have become an indispensable part of electronic products, and its design and application have become a necessary skill for electronic engineers.
CPLD is a kind of digital integrated circuit that users construct logic functions according to their own needs. The basic design method is to use the integrated development software platform to generate corresponding target files using schematics, hardware description languages, etc., and transfer the code to the target chip through the download cable ("in-system" programming) to realize the designed digital system .
Take the answering machine as an example to talk about its design (decoration) process, that is, the design process of the chip. Most of CPLD's work is done on the computer. Open the integrated development software (Altera Max pluxII) → draw the schematic diagram, write the hardware description language (VHDL, Verilog) → compile → give the input excitation signal of the logic circuit, perform simulation, check whether the logic output result is correct → perform pin input 3. Output lock (64 input pins and output pins of 7128 can be set as required) → generate code → transfer and store the code in the CPLD chip through the download cable. The pins of the 7128 chip have been led out. Connect the digital tube, the answer switch, the indicator light, and the buzzer to the chip board through the wire, and test the power. When the answer switch is pressed, the corresponding indicator should be on. In the future, after the referee gives points, see if the digital display shows that the result is correct. If a problem is found, the schematic or hardware description language can be revised to improve the design. After the design is completed, such as mass production, you can directly copy other CPLD chips, that is, write the code. If you want to design other chips, such as traffic light design, you need to redraw the schematic diagram or write a hardware description language, repeat the above process to complete the design. This modified design is equivalent to renovating the house, which can be carried out tens of thousands of times for CPLD.
After decades of development, many companies have developed CPLD programmable logic devices. The more typical ones are the products of three authoritative companies in the world, Altera, Lattice and Xilinx. Here are the commonly used chips: Altera EPM7128S (PLCC84)
Lattice LC4128V (TQFP100)
Xilinx XC95108 (PLCC84)
The identification and classification of FPGA and CPLD are mainly based on their structural characteristics and working principles. The usual classification method is:
The devices that form logical behavior in the product term structure are called CPLDs, such as Lattice's ispLSI series, Xilinx's XC9500 series, Altera's MAX7000S series, and Lattice (formerly Vantis) Mach series.
The devices that form logical behavior in the form of a table lookup method are called FPGAs, such as Xilinx's SPARTAN series, Altera's FLEX10K or ACEX1K series.
Although FPGA and CPLD are programmable ASIC devices and have many common characteristics, due to the differences in structure of CPLD and FPGA, they have their own characteristics:
① CPLD is more suitable for completing various algorithms and combinational logic, FPGA is more suitable for completing sequential logic. In other words, FPGA is more suitable for the structure with rich triggers, and CPLD is more suitable for the structure with limited triggers and rich product terms.
② CPLD's continuous wiring structure determines that its timing delay is uniform and predictable, while FPGA's segmented wiring structure determines its delay unpredictability.
③ FPGA has greater flexibility than CPLD in programming. CPLD is programmed by modifying the logic function with a fixed internal circuit, FPGA is mainly programmed by changing the wiring of internal wiring; FPGA can be programmed under the logic gate, and CPLD is programmed under the logic block.
④ FPGA has higher integration than CPLD and has more complicated wiring structure and logic implementation.
⑤ CPLD is more convenient to use than FPGA. CPLD programming uses E2PROM or FASTFLASH technology, no external memory chip is needed, and it is easy to use. The FPGA programming information needs to be stored in an external memory, the method of use is complex.
⑥ The speed of CPLD is faster than that of FPGA, and has greater time predictability. This is because FPGA is gate-level programming, and distributed interconnection is used between CLBs, while CPLD is logic block-level programming, and the interconnection between its logic blocks is lumped.
⑦In the programming method, CPLD is mainly based on E2PROM or FLASH memory programming, the number of programming times can reach 10,000 times, the advantage is that the programming information is not lost when the system is powered off. CPLD can be divided into two types: programming on the programmer and programming in the system. Most FPGAs are based on SRAM programming. The programming information is lost when the system is powered off. Each time the power is turned on, the programming data needs to be rewritten into the SRAM from outside the device. The advantage is that it can be programmed any number of times and can be quickly programmed in the work, so as to achieve dynamic configuration at the board level and system level.
⑧CPLD has good confidentiality and FPGA has poor confidentiality.
⑨ In general, the power consumption of CPLD is greater than that of FPGA, and the higher the integration, the more obvious.
CPLD CoolRunner Family 4K Gates 128 Macro Cells 0.5um Technology 5V 84-Pin PLCC
FPGA XC5200 Family 10K Gates 784 Cells 83MHz 0.5um Technology 5V 160-Pin PQFP
CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 256MHz 0.18um Technology 1.8V 208-Pin PQFP
FPGA Spartan-3A Family 400K Gates 8064 Cells 667MHz 90nm Technology 1.2V 400-Pin FBGA
FPGA Spartan-3A Family 400K Gates 8064 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA