The SSTL interface standard is also one of the standards recognized by JEDEC. The standard specifically targets high-speed memory (especially SDRAM) interfaces. SSTL stipulates switch characteristics and special termination schemes, and it can obtain operating frequencies up to 200MHz.
STUB SERIES TERMINATED LOGIC stub series termination logic
The SSTL interface standard will be the first choice for next-generation high-speed memory interfaces. There are two SSTL standards. SSTL_3 is a 3.3V standard; SSTL_2 is a 2.5V standard. For these two standards, JEDEC defines a number of different levels according to the characteristics of the output buffer (level I and level II are the most popular).
The main application of the SSTL_2/3 I/O standard is to interface with SDRAM. High-end servers, laptop computers, and various network products, such as ATM switches, IP routers/switches, and frame relay interfaces, all require on-board SDRAM. When using high-speed SDRAM, you can choose the SSTL interface standard.
Common SSTL interfaces are, SSTL-2, SSTL-3, SSTL-18.
DDR uses SSTL-2, SST common SSTL interface L-3, DDR2 uses SSTL-18, SSTL-2, and DDR3 uses SSTL-15.
FPGA XC5200 Family 23K Gates 1936 Cells 83MHz 0.5um Technology 5V 208-Pin HSPQFP EP
FPGA Spartan-3 Family 50K Gates 1728 Cells 725MHz 90nm Technology 1.2V 100-Pin VTQFP
FPGA Spartan-3A Family 50K Gates 1584 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
FPGA Spartan-3A Family 50K Gates 1584 Cells 667MHz 90nm Technology 1.2V 100-Pin VTQFP
FPGA Spartan-3A Family 50K Gates 1584 Cells 770MHz 90nm Technology 1.2V 100-Pin VTQFP