The shift register look-up table SRL uses the look-up table as a shift register SRL16 is an SRL macro. This shift register can achieve serial shifts of up to 16 clock cycles. For each look-up table, SRL can be implemented without any reset. The function of serial input and serial output is a simple shift register function. However, SRL can be used to initialize the data at power-up. The INIT attribute is used in the ucf file and each register in the SRL can be dynamically read in Virtex- The macro SRLC16 in II has two outputs available for a dynamically addressable output and a final output.
Xilinx QFP100
FPGA Spartan-3 Family 50K Gates 1728 Cells 725MHz 90nm Technology 1.2V 144-Pin TQFP EP
FPGA Spartan-3A Family 50K Gates 1584 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
FPGA Spartan-3A Family 50K Gates 1584 Cells 667MHz 90nm Technology 1.2V 144-Pin TQFP
FPGA Spartan-3A Family 50K Gates 1584 Cells 770MHz 90nm Technology 1.2V 144-Pin TQFP
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