Static random access memory (Static Random-Access Memory, SRAM) is a type of random access memory. The so-called "static" means that the data stored in this memory can be kept constant as long as it is powered on. In contrast, the data stored in dynamic random access memory (DRAM) needs to be updated periodically. However, when the power supply is stopped, the data stored in the SRAM will still disappear (called volatile memory), which is different from the ROM or flash memory that can store data after the power is turned off.
SRAM can save the data stored in it without refresh circuit. And RAM (Dynamic Random Access Memory) needs to be refreshed and charged every other time, otherwise the internal data will disappear, so SRAM has higher performance, but SRAM also has its shortcomings, that is, its low integration level, power Compared with DRAM, DRAM with the same capacity can be designed with a smaller volume, but SRAM requires a large volume. Silicon wafers of the same area can make DRAM of larger capacity, so SRAM is more expensive.
One is the cache between the CPU and the main memory. It has two specifications: one is the cache (Cache Memory) fixed on the motherboard; the other is the COAST (Cache On A) inserted in the card slot Stick) cache for expansion. In addition, in the circuit of CMOS chip 146818, it also has a 128-byte SRAM with a smaller capacity to store the configuration data we set. In addition, in order to speed up the transfer of data within the CPU, since the 80486CPU, a cache is also designed inside the CPU, so in the Pentium CPU, there are the terms L1 Cache (level 1 cache) and L2Cache (level 2 cache) In general, L1 Cache is built inside the CPU, and L2 Cache is designed outside the CPU, but Pentium Pro designs both L1 and L2 Cache inside the CPU, so Pentium Pro has a larger volume. Pentium II moved the L2 Cache to a black box outside the CPU core. SRAM is obviously fast and does not require a refresh operation, but it also has other disadvantages, namely, high price and large size, so it cannot be used as a main memory with a large amount on the motherboard.
SRAM is mainly used for Level 2 Cache. It uses transistors to store data. Compared with DRAM, SRAM is faster, but the capacity of SRAM is smaller than other types of memory in the same area.
SRAM is fast but expensive, and generally uses small-capacity SRAM as a cache between a higher-speed CPU and a lower-speed DRAM. SRAM also has many types, such as AsyncSRAM (Asynchronous SRAM, asynchronous SRAM), Sync SRAM (Synchronous SRAM , Synchronous SRAM), PBSRAM (Pipelined Burst SRAM, pipelined burst SRAM), and INTEL's CSRAM, which did not disclose details.
The basic SRAM architecture is shown in Figure 1. SRAM can be generally divided into five parts: memory cell array (core cells array), row/column address decoder (decode), sensitive amplifier (Sense Amplifier), control circuit (control circuit), buffer/driver circuit (FFIO). SRAM is a static storage method, using a bistable circuit as a storage unit. SRAM does not need to be constantly refreshed like DRAM, and its working speed is faster, but due to the large number of storage unit devices, the integration is not very high, and the power consumption is also large.
The working principle of SRAM:
Suppose that you are going to write "1" to the 6T memory cell in Figure 2. First, input a certain set of address values into the row and column decoders, select a specific cell, and then enable the write enable signal WE, which will be written The data "1" is changed to "1" and "0" by the write circuit and then added to the two bit lines BL, BLB of the selected cell. At this time, WL=1 of the selected cell, the transistors N0, N5 are turned on, and BL The signals on BLB are sent to points Q and QB respectively, so that Q=1 and QB=0, so that the data "1" is latched in the latch formed by the transistors P2, P3, N3 and N4. The process of writing data "0" is similar.
The reading process of SRAM takes reading "1" as an example, selects a column bit line through the decoder to pre-charge BL and BLB to the power supply voltage VDD, and after pre-charging is completed, selects a row through the row decoder, then a A memory cell is selected, because it contains "1", then WL=1, Q=1, QB=0. The transistors N4 and N5 are turned on, and current flows to the ground through N4 and N5, thereby reducing the potential of BLB, and the potential difference between BL and BLB generates a voltage difference. When the voltage difference reaches a certain value, the sensitivity amplifier is turned on, the voltage is amplified, and then sent to the output Circuit, read data.
Non-volatile SRAM (Non-volatile SRAM, nvSRAM) has the standard function of SRAM, but can retain its data when the power supply is lost. Non-volatile SRAM is used in critical occasions such as network, aerospace, medical, etc.-keeping data is critical and it is impossible to use batteries.
Asynchronous SRAM (Asynchronous SRAM) capacity from 4 Kb to 64 Mb. The fast access of SRAM makes asynchronous SRAM suitable for the main memory of small embedded processors with small caches. Such processors are widely used in industrial electronic equipment, measuring equipment, hard disks, network equipment, etc.
Bipolar junction transistors (for TTL and ECL)-very fast but huge power consumption
MOSFET (for CMOS)-The type detailed in this article, low power consumption, is now widely used.
Asynchronous-Independent clock frequency, read and write is controlled by address line and control enable signal.
Synchronization—All work begins with the edge of the clock pulse, and the address line, data line, and control line all cooperate with the clock pulse.
Zero bus turnaround (ZBT)—The clock cycle required for the SRAM bus from writing to reading and from reading to writing is 0
Synchronous burst SRAM (synchronous-burst SRAM, syncBurst SRAM)—
DDR SRAM—synchronous, single-port read/write, dual data rate I/O
QDR SRAM (Quad Data Rate (QDR) SRAM)-synchronous, separate read/write port, read and write 4 words at the same time.
Binary SRAM
Ternary computer SRAM
SRAM (Static RAM) is static RAM. It is also composed of transistors. On represents 1 and off represents 0, and the state remains until a change signal is received. These transistors do not need to be refreshed, but they will lose information like DRAM when they are shut down or powered off. The speed of SRAM is very fast, usually can work at 20ns or faster. A DRAM memory cell requires only one transistor and a small capacitor. Each SRAM cell requires four to six transistors and other parts. Therefore, in addition to being more expensive, SRAM chips are also larger in shape and take up more space than DRAM. Due to the difference in appearance and electrical, SRAM and DRAM are not interchangeable.
The high speed and static characteristics of SRAM make them commonly used as cache memory. The computer's motherboard has a Cache socket.
As shown in the figure is a block diagram of SRAM structure. It can be seen from the above figure that SRAM is generally composed of five major parts, namely, memory cell array, address decoder (including row decoder and column decoder), sensitive amplifier, control circuit and buffer/drive circuit. In the figure, A0-Am-1 is the address input terminal, CSB. WEB and OEB are the control terminals, which control the read and write operations, and are low level effective, and 1100-11ON-1 are the data input and output terminals. Each memory cell in the memory array shares electrical connections with other cells in rows and columns, where the horizontal lines are called "word lines", and the vertical lines of data flowing into and out of the memory cells are called " Bit line". The specific word line and bit line can be selected through the input address. The intersection of the word line and bit line is the selected memory cell. Each memory cell is uniquely selected in this way, and then read and write it operating. Some memories are designed for multi-bit data such as 4 or 8 bits to be input and output at the same time. In this case, 4 or 8 memory cells will be selected at the same time for read and write operations as described above.
In SRAM, the array of memory cells arranged in a matrix is surrounded by a decoder and an interface circuit with external signals. The memory cell array is usually in the form of a square or matrix to reduce the entire chip area and facilitate data access. Taking an SRAM with a storage capacity of 4K bits as an example, a total of 12 address lines are required to ensure that each memory cell can be selected (=4096). If the memory cell array is arranged as a long strip containing only one column, a 12/4K bit decoder is required, but if it is arranged as a square containing 64 rows and 64 columns, then only a 6/64 bit is required Row decoder and a 6/64-bit column decoder. The row and column decoders can be arranged on both sides of the memory cell array. There are 4096 intersections in 64 rows and 64 columns, one for each point Storage bit. Therefore, arranging memory cells in a square shape greatly reduces the entire chip area than arranging them in a row. In addition to the singular shape and large area, the storage cell arrangement has a shortcoming, that is, the connection between the storage unit and the data input/output terminal in the upper row of the column becomes very long, especially for capacity comparison For large memory, the situation is more serious, and the delay of the connection is at least linearly related to its length. The longer the connection, the greater the delay on the line, so it will cause a decrease in read and write speeds. The inconsistency of different memory cell connection delays, these are to be avoided in the design.
SRAM is more expensive than DRAM, but faster and has lower power consumption (only in idle state). Therefore, SRAM is preferred for high bandwidth requirements. SRAM is easier to control than DRAM, and it is more random access. Due to the complex internal structure, SRAM occupies a larger area than DRAM, so it is not suitable for higher storage density and low cost applications, such as PC memory.
Clock frequency and power consumption
SRAM power consumption depends on its access frequency. If you use high frequency to access SRAM, its power consumption is much larger than DRAM. Some SRAMs consume several watts of power at full bandwidth. On the other hand, if the SRAM is used for a microprocessor with a moderate clock frequency, its power consumption will be very small, and the power consumption can be ignored in the idle state-a few microwatt levels.
SRAM is used for:
General products
Asynchronous interface, such as a 28-pin 32Kx8 chip (often named XXC256), and similar products up to 16 Mbit per chip
synchronous interface, usually used as cache and other applications that require burst transmission, up to 18 Mbit (256Kx72) per slice
Integrated in the chip
RAM or cache as a microcontroller (usually from 32 bytes to 128 kilobytes)
As the main caches of powerful microprocessors, such as x86 series and many other CPUs (from 8kiB to several million bytes)
As a register (see register file)
Used for specific ICs or ASIC (usually in the order of several kilobytes)
For FPGA and CPLD
Embedded application
Many subsystems used in industry and science, automotive electronics, etc. use SRAM. Many modern devices are embedded with several kilobytes of SRAM. Virtually all modern devices that implement electronic user interfaces may use SRAM, such as toys. Digital cameras, mobile phones, audio synthesizers, etc. often use several megabytes of SRAM. Real-time signal processing circuits often use dual-ported (dual-ported) SRAM.
For computers
SRAM is used for PCs, workstations, routers and peripherals: internal CPU cache, SRAM cache for external burst mode, hard disk buffer, router buffer, etc. LCD monitors or printers also often use SRAM to cache data. Small buffers made of SRAM are also common in CDROM and CDRW drives, usually 256 KiB or more, used to buffer audio track data. Cable modems and similar devices connected to computers also use SRAM.
Lovers
Amateurs who build their own processors prefer SRAM because of its easy-to-use working interface. There is no refresh cycle required by DRAM; the address bus and data bus are accessed directly instead of multiple access separately like DRAM. SRAM usually only needs 3 control signals: Chip Enable (CE), Write Enable (WE) and Output Enable (OE). For synchronous SRAM, a clock signal (Clock, CLK) is also required.
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