Simulation primitives These simulation primitives are used to perform timing simulation for a design implemented with Xilinx devices.
1. D:\Xilinx\13.3\ISE_DS\ISE\verilog\mti_se\6.5e\nt\simprims_ver
For post-layout simulation
2. D:\Xilinx\13.3\ISE_DS\ISE\verilog\mti_se\6.5e\nt\xilinxcorelib_ver
Used to compile and simulate programs with IP core
3. D:\Xilinx\13.3\ISE_DS\ISE\verilog\mti_se\6.5e\nt\unisims_ver
Used for functional simulation (behavior simulation), used for the post-synthesis mode generated after XST synthesis.
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um Technology 1.8V 324-Pin FBGA
Xilinx QFP100
FPGA Spartan-3 Family 50K Gates 1728 Cells 725MHz 90nm Technology 1.2V 144-Pin TQFP EP
FPGA Spartan-3A Family 50K Gates 1584 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
FPGA Spartan-3A Family 50K Gates 1584 Cells 667MHz 90nm Technology 1.2V 144-Pin TQFP
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