The standard cell ASIC ASIC uses standard logic cells to achieve a compact package. A standard cell ASIC uses blank wafers instead of a partially fabricated standard cell ASIC. It is characterized by high initial cost and long development time. The largest possible density and highest performance are the cheapest and most effective when the volume is large.
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 217MHz 0.18um Technology 1.8V 256-Pin FTBGA
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 217MHz 0.18um Technology 1.8V 144-Pin TQFP EP
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um Technology 1.8V 324-Pin FBGA
FPGA Spartan-3 Family 50K Gates 1728 Cells 725MHz 90nm Technology 1.2V 144-Pin TQFP EP