Relatively placed macros Relatively placed macros use RLOC constraints to group related logic together to reduce the amount and delay associated with routing.
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 217MHz 0.18um Technology 1.8V 324-Pin FBGA
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 217MHz 0.18um Technology 1.8V 208-Pin PQFP
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um Technology 1.8V 324-Pin FBGA
FPGA XC5200 Family 23K Gates 1936 Cells 83MHz 0.5um Technology 5V 208-Pin HSPQFP EP
FPGA Spartan-3 Family 50K Gates 1728 Cells 725MHz 90nm Technology 1.2V 132-Pin CSBGA
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