HDL

History

The development of hardware description language HDL has more than 20 years of history, and has been successfully applied to all stages of design: modeling, simulation, verification and synthesis. By the 1980s, hundreds of hardware description languages had appeared, which had greatly promoted and promoted design automation. However, these languages generally face specific design fields and levels, and many languages make users confused. Therefore, there is an urgent need for a design-oriented multi-domain, multi-level and generally accepted standard hardware description language. In the late 1980s, VHDL and Verilog HDL languages adapted to this trend and became the IEEE standard.

With the emergence of system-level FPGAs and system chips, coordinated software and hardware design and system design have become increasingly important. The traditional hardware design is more and more inclined to be combined with system design and software design. In order to adapt to the new situation, the hardware description language has developed rapidly, and many new hardware description languages have appeared, such as Superlog, SystemC, Cynlib and so on.

Purpose

Since the 1970s, the complexity of integrated circuits has increased dramatically in accordance with the trend of Moore's Law in the semiconductor industry. The workload of circuit designers is increasing, which makes them have to abandon specific electronic components, such as CMOS and bipolar transistors, to start the design of complex circuits. The focus of the design flow begins to shift to the data flow of the circuit system and information about timing. This level of design abstraction is called the "register transfer level." Designers can use hardware description language to focus on the design of circuit logic functions and timing without having to consider specific device manufacturing processes and their impact on circuit functions from the beginning.

Structure

The hardware description language is a standard text description of the structure and behavior of the circuit system. Hardware description languages, like some parallel programming languages, have an expression of parallelism. However, unlike most programming languages used for software design, hardware description languages can describe the timing behavior of hardware systems at different times, and timing is one of the important properties of hardware circuits. In computer-aided design, the hardware description language code used to describe the wiring in circuit modules and the interconnection between modules at various levels is called a "netlist." The hardware description language can describe circuits at several different levels: structure level (or logic gate level), behavior level, and register transfer level. A hardware description language that implements the same function can also use any level of hardware description language Code to describe. Through logic synthesis, the latter two levels of hardware description language codes can be converted to low-level gate-level descriptions, but using tools from different vendors and using different comprehensive setting strategies may produce different results.

Before implementing specific hardware circuits, designers can use hardware description languages for simulation. In the process of hardware implementation, the source file of the hardware description language is usually converted into an intermediate file similar to an executable file, which can explain the semantics of various codes and statements of the hardware description language. Because of this, the hardware description language has some properties similar to software programming languages, but in general, it still belongs to the category of specification languages and modeling languages. Analog circuits also have their own hardware description languages, but they differ significantly from digital circuits.

Comparison with control flow language

You can use the characteristics of the traditional programming language control flow to refer to the data flow nature of the hardware. For example, C++ (such as SystemC) containing a specific enhanced class library can achieve this purpose. Nevertheless, the programming language used for software design cannot describe the timing properties of the circuit, which results in the software programming language not replacing the dedicated hardware description language. Before the emergence of the more prominent hardware verification language, SystemVerilog, people used C++ and some logic simulation tools to work together to realize the idea of object-oriented programming in hardware verification.

Some subsets of the hardware description language are synthesizable, which means that logic synthesis tools can be used to "infer" the corresponding functions of these codes by "reading" the code at the behavior level and the register transfer level, thus giving an optimized Netlist of circuit connections. Logic synthesis tools (such as Synopsys' Design Compiler, etc. or Cadence's RTL Compiler) usually simplify the logic functions defined by the designer, so as to avoid redundant logic gate-level netlists. Hardware description language codes that contain delays (such as the #5 code in Verilog) are usually not synthesizable, that is, this part of the code will be ignored during the logic synthesis process. This type of code plays a more significant role in hardware verification. In addition, there are other parts of the code structure that are not synthesizable.

Design with hardware description language

By using hardware description language, the design efficiency of integrated circuits (especially modern digital circuits) can be greatly improved. Most designers start designing from design behavior goals or high-level architectural diagrams. The control decision structure of the circuit system is based on the flow chart and state diagram. The process of writing the hardware description language code is related to the characteristics of the target circuit and the designer's programming style. The hardware description language may be a high-level algorithm description. Designers often use scripting languages (such as Perl, Python) to generate repetitive circuit structures in hardware description languages. The programming of the hardware description language can be completed in some code editors. These software usually provide auxiliary functions such as automatic indentation and reserved word highlighting.

Subsequently, the hardware description language code will go through the review stage. Before logic synthesis, the electronic design automation software will perform a series of automatic checks, such as scanning for grammatical errors in the hardware description language code. The automatic inspection program will present the code that violates the rules in the report, and indicate their potential harm. Hardware logic errors in the code will also be checked at this stage. These review processes can minimize errors caused by the code after synthesis.

In the industrial world, hardware description language design generally stops at the completion of synthesis. Once the logic synthesis tool maps the hardware description language code to the logic gate-level netlist, the netlist will be sent to the subsequent back-end process production line. According to different devices used, such as field programmable logic gate array (FPGA), application specific integrated circuit (ASIC), gate array (Gate array), application specific integrated circuit standard components (Standard cell), the actual circuit hardware manufacturing process may be different , But hardware description languages generally do not pay much attention to back-end processes. Generally speaking, as the design process gradually shifts to physical implementation, the focus of the design database will turn to device manufacturing process-related information, which is usually provided by hardware manufacturers. The hardware description language code written by designers does not need to include this aspect. information. Finally, integrated circuits are physically realized.