Pin locking is the act of placing input and output signals on specific pins in a component. Process by which a signal is given a location on a specific FPGA package pin. Because FPGAs are fully programmable, designers can place signals on any specific pin in the device. Note that it is generally recommended to establish a horizontally distributed data flow in the device. The lowest bit of the bus is placed in the lower part of the left and right sides of the chip. This is often because the carry logic carry chain is distributed vertically from bottom to top in the chip.
FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 208-Pin PQFP
FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
FPGA Spartan-XL Family 10K Gates 466 Cells 250MHz 3.3V 100-Pin VTQFP
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 144-Pin TQFP
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 217MHz 0.18um Technology 1.8V 256-Pin FTBGA
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