Positive-emitter coupling logic. Two signal lines are required to send each data bit. For each input or output, this standard specifies two pins. The voltage slew rate between these two signal lines is approximately 850 mV. It does not need to use the reference voltage VREF or the board-level termination voltage V TT. LVPECL requires external resistor termination.
FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 132-Pin CSBGA
FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
FPGA Spartan-XL Family 10K Gates 466 Cells 250MHz 3.3V 100-Pin VTQFP
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 208-Pin PQFP
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 217MHz 0.18um Technology 1.8V 324-Pin FBGA
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