Placement and routing. It is the act of putting logic into silicon and routing signals between logic to meet timing requirements.
In this chapter we address the physical design of the flow layer, which consists of the placement and routing tasks. Placement decides the location of components on the chip, and routing decides the channels interconnecting the components, and their layout on the chip. The physical design of the control layer is presented in the next chapter. We present several algorithms for placement and routing. Placement is solved using a simulated annealing-based metaheuristic, and we propose several cost functions to evaluate the fitness of a placement solution. For routing, we adapt several algorithms from the microelectronics VLSI literature and show how they can be applied to mVLSI biochips. The proposed algorithms are evaluated using several benchmarks.
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 256-Pin FTBGA
FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 132-Pin CSBGA
FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
FPGA Spartan-XL Family 10K Gates 466 Cells 250MHz 3.3V 100-Pin VTQFP
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 208-Pin PQFP