Programmable array logic. It is a type of programmable logic device (PLD) that contains a programmable AND gate array and a predefined OR gate array (only the AND gate connection can be programmed). PAL is usually arranged to provide products and sum-of-products ( SOP) logical expression.
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 256-Pin FTBGA
FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 132-Pin CSBGA
FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 208-Pin PQFP
FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 100-Pin VTQFP
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 208-Pin PQFP
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