This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.

Home > Wiki encyclopedia > pad-to-pad

pad-to-pad

It is a timing specification that covers the path from the input pin through the combinational logic to the output pin. Pin-to-pin constraints do not cross any registered boundaries.

Other Wikis

optimize
one-hot
OFFSET OUT
OFFSET IN
nW
PAL
P&R
PAR
PCI
period

ASSOCIATED PRODUCTS

XC2C384-10FT256C

CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 256-Pin FTBGA
XC2C384-10PQ208C

CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 208-Pin PQFP
XC3S50-4PQ208C

FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 208-Pin PQFP
XC3S50-4TQG144I

FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
XCS10XL-5VQG100C

FPGA Spartan-XL Family 10K Gates 466 Cells 250MHz 3.3V 100-Pin VTQFP