XADC includes a dual 12-bit, 1 megasample per second (MSPS) ADC and on-chip sensor. These ADCs provide a common high-precision analog interface for a range of applications. The dual ADC supports multiple operating modes, and the ADC can access up to 17 external analog input channels.
XADC includes multiple on-chip sensors that support measuring on-chip power supply voltage and chip temperature. The ADC conversion data is stored in special registers called status registers. ADC conversion data can be accessed through JTAG TAP.
Compared with xilinx's V5 and V6 series, the XADC module in the 7 series FPGA contains a large number of new functions and enhanced functions. The new functions are enabled by initializing previously undefined status registers.
All XADC dedicated pins are located in bank 0. There are two recommended configurations. On the left, XADC is powered by VCCAUX (1.8V) and uses an external 1.25V reference voltage source. The external reference provides the best performance in terms of accuracy and thermal drift. Ferrite beads are used to isolate analog and digital grounds. The additional low-pass filter of the VCCAUX power supply will also improve ADC performance. The on-chip reference voltage source can also be used for the ADC. To enable the on-chip reference source, the VREFP pin must be grounded, as shown on the right. If you only need basic on-chip heat and power monitoring, using an on-chip voltage reference can provide good performance.
① AD0P_ to AD15P/AD0N to _AD15N: These are multi-function pins that can support analog input or can be used as conventional digital I/O. These pins support up to 16 positive input terminals of differential auxiliary analog input channels (VAUXP / VAUXN). The analog input channel is very flexible and supports multiple analog input signal types.
② VP/N_0: This is the positive input terminal of the dedicated differential analog input channel (VP / VN). The analog input channel is very flexible and supports multiple analog input signal types.
Kintex-7 devices do not support auxiliary channels 6, 7, 13, 14, and 15. Some Virtex-7, Artix-7, Spartan-7, and Zynq-7000 SoC device packaging options may not yet support some auxiliary analog channels. For details, see the manual.
In addition to a single dedicated analog input pair (VP/VN), the external analog input also uses dual-purpose I/O. When XADC is instantiated in the design, these FPGA digital I/Os are instantiated as analog inputs, respectively. Up to 16 auxiliary analog inputs can be provided. All analog input channels are differential, and generally, the auxiliary analog inputs are equally distributed on BANK15 and BANK35.
Compared to ISE tools, Vivado® tools support auxiliary analog inputs differently. The auxiliary analog input does not require any user-specified constraints or pin positions in the ISE tool. ISE external auxiliary input does not require I/O standard settings to be added to the constraint file (UCF) or PlanAhead™ design tool. In the Vivado design tool, auxiliary analog inputs must be assigned to the relevant pin locations.
If XADC is not instantiated in the design, the only way to access this information is through JTAG. The XADC port is as follows, the meaning of the port can be read with reference to the manual, and will not be described here:
FPGA Spartan-3A Family 400K Gates 8064 Cells 667MHz 90nm Technology 1.2V 320-Pin FBGA
FPGA Spartan-3A Family 400K Gates 8064 Cells 667MHz 90nm Technology 1.2V 256-Pin FTBGA
CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 256MHz 0.18um Technology 1.8V 144-Pin TQFP
CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 152MHz 0.18um Technology 1.8V 132-Pin CSBGA
FPGA Spartan-3A Family 400K Gates 8064 Cells 770MHz 90nm Technology 1.2V 400-Pin FBGA