It is a timing constraint that covers the path from the synchronization element to the output pin.
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 324-Pin FBGA
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 256-Pin FTBGA
FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 132-Pin CSBGA
FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 208-Pin PQFP
FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 100-Pin VTQFP
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