This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.

Home > Wiki encyclopedia > OFFSET IN

OFFSET IN

It is a timing constraint that covers the path from the input pin to the synchronization element.

Other Wikis

XC2C32A-6VQG44I

CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 200MHz 0.18um, CMOS Technology 1.8V 44-Pin VQFP
XC2C384-10FT256C

CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 256-Pin FTBGA
XC2C384-10PQ208C

CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 208-Pin PQFP
XC3S50-4PQ208C

FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 208-Pin PQFP
XC3S50-4TQG144I

FPGA Spartan-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP