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NGDBuild

NGDBuild is the converted command line name.

Xilinx ISE中ERROR:NgdBuild:604

Call the symbol of EDK in the SCH of ISE, the function of EDK is also very simple, that is, the CPU prints a string of characters through the string

   First, I build an ISE project

   Create another source sch type and set it to the top level, named top.sch

   Build another source type as Embedded processor and name it mycpu

   Then EDK is automatically turned on, I add peripherals according to the wizard, set the clock, until finish

   Then generate netlist, generate lib and bsp, builder all user app under edk.

   Go back to ISE, select mycpu, create schematic symbol, and add the symbol to top.sch

   Then add ports and constrain pins

   Finally, synthesize, generate bit

   But when it comes to Translate, it fails, and the following error is reported

Processing BMM file "edkBmmFile.bmm" ...

ERROR:NgdBuild:989-Failed to process BMM information edkBmmFile.bmm

Checking expanded design ...

ERROR:NgdBuild:604-logical block'microblaze_0/proc_sys_reset_0' with type

   'proc_sys_reset_0_wrapper' could not be resolved. A pin name misspelling can

   cause this, a missing edif or ngc file, case mismatch between the block name

   and the edif or ngc file name, or the misspelling of a type name. Symbol

   'proc_sys_reset_0_wrapper' is not supported in target'spartan 3a'.

solve:

(1) Add the path of the implementation subdirectory of the EDK project to the attribute "-sd: Macro search Path" of ngdbuild in ISE.

You can use relative paths.

(2) It can be regarded as a BUG of the software, and the official has a related explanation.

http://www.xilinx.com/support/answers/38262.htm

According to the official solution

Add (* box_type = "user_black_box" *)

That’s fine, but I don’t understand the meaning of this sentence

Under the processes column, select Translate, right-click process propreties...

The Translate Properties dialog box pops up,

Add the path of the implementation subdirectory of the EDK project to the -sd macro search path, it will be fine, but the NGC file is still not found

Official explanation:

Description

The following error occurs when the implementation process runs:

"ERROR:NgdBuild:989-Failed to process BMM information edkBmmFile.bmm"

"ERROR:NgdBuild:604-logical block'Inst_edksub/proc_sys_reset_0' with type'proc_sys_reset_0_wrapper' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol'proc_sys_reset_0_wrapper' is not supported in target'virtex5'."

"ERROR:NgdBuild:604-logical block'Inst_edksub/mdm_0' with type'mdm_0_wrapper' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol'mdm_0_wrapper' is not supported in target'virtex5'."

These errors do not appear in 12.1.

Solution

The difference between 12.1 and 12.2 is:

*                              12.1 Project Navigator copies all NGC files generated by XPS in the implementation folder of the current XPS project into the top ISE project.

*                              12.2 Project Navigator copies only one NGC file (top level NGC file of EDK submodule) into ISE project.

Solution 1

Add the user_black_box attribute to your HDL code.  If you have your EDK project instantiated as system:

VHDL

attribute box_type : string;

 attribute box_type of system : component is "user_black_box";

Verilog

(* box_type = "user_black_box" *)

system u1 (. . . . );

Solution 2

Add "Macro Search Path" = XPS project implementation sub-directory to Translate Properties so that NGDBuild can find the netlists.

Run global optimization

For designs that include IP cores or other netlists, the NGD file generated after the implementation of the conversion (NGDBuild) stage indicates that the entire design is fully compiled for the first time. Global optimization is a new function added in Map 7.1.01i. It will assemble the complete design and try to improve the design performance by re-optimizing the combination and register logic. Global optimization (type map -global_opt on the command line) shows that it can increase the design clock frequency by an average of 7%.

There are also two options that allow you to further control the completion of optimization at this stage: timing adjustment (retiming) (map -retiming) will move registers back and forth to balance the combinatorial logic delay, and equivalent register removal (map -equivalent_register_removal) will pass redundant I functionally delete the register.


Run global optimization

For designs that include IP cores or other netlists, the NGD file generated after the implementation of the conversion (NGDBuild) stage indicates that the entire design is fully compiled for the first time. Global optimization is a new function added in Map 7.1.01i. It will assemble the complete design and try to improve the design performance by re-optimizing the combination and register logic. Global optimization (type map -global_opt on the command line) shows that it can increase the design clock frequency by an average of 7%.

There are also two options that allow you to further control the completion of optimization at this stage: timing adjustment (retiming) (map -retiming) will move registers back and forth to balance the combinatorial logic delay, and equivalent register removal (map -equivalent_register_removal) will pass redundant I functionally delete the register.


Run global optimization

For designs that include IP cores or other netlists, the NGD file generated after the implementation of the conversion (NGDBuild) stage indicates that the entire design is fully compiled for the first time. Global optimization is a new function added in Map 7.1.01i. It will assemble the complete design and try to improve the design performance by re-optimizing the combination and register logic. Global optimization (type map -global_opt on the command line) shows that it can increase the design clock frequency by an average of 7%.

There are also two options that allow you to further control the completion of optimization at this stage: timing adjustment (retiming) (map -retiming) will move registers back and forth to balance the combinatorial logic delay, and equivalent register removal (map -equivalent_register_removal) will pass redundant I functionally delete the register.


Run global optimization

For designs that include IP cores or other netlists, the NGD file generated after the implementation of the conversion (NGDBuild) stage indicates that the entire design is fully compiled for the first time. Global optimization is a new function added in Map 7.1.01i. It will assemble the complete design and try to improve the design performance by re-optimizing the combination and register logic. Global optimization (type map -global_opt on the command line) shows that it can increase the design clock frequency by an average of 7%.

There are also two options that allow you to further control the completion of optimization at this stage: timing adjustment (retiming) (map -retiming) will move registers back and forth to balance the combinatorial logic delay, and equivalent register removal (map -equivalent_register_removal) will pass redundant I functionally delete the register.


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