Netlist

Parsing

Modern digital integrated circuit design methods come from a summary of traditional design methods and the introduction of computer software technology. When the circuit performance requirements do not reach the process limit, no special design is required for each unit circuit. A variety of basic unit circuits (cells) can be designed first, including schematics and layouts, to form a standard cell library, and then Use the cells in the library to implement complex logical relationships. This method makes automated design possible. Even in the fully customized design, the description of the circuit function is hierarchical, rather than directly described as a transistor network. With the standard cell library, a circuit can be understood as a netlist composed of standard cells, which means that the "description level" has been upgraded from the transistor level to the "gate level".

The complicated circuit is still difficult to see the logic function at the "gate level", which requires a higher level of description. A complex digital circuit system can be understood as composed of several modules with typical logic functions and a control circuit. Common modules include registers, counters, arithmetic and logic operation units, and memory. The control circuit is a finite state machine. Under the effect of the clock, the state machine continuously changes the state according to the current state and the input signal, and at the same time generates the output signal to control the work of each logic module. This level of description is called the "architecture level" and is the most important design level. The highest level of description is the system level. At this level, only the functions of the system, external interfaces, and main functional modules are generally defined. The lowest level of description is the layout, which is actually a set of geometric figures, and a lithographic version can be generated according to the layout. A design actually always starts from the system level, then the architecture level, gate level, transistor level, and finally the layout level. In the traditional design flow, the verifiable design description starts at the transistor level, using transistors to form logic gates, and then logic gates to form functional modules, and finally connected into a system.

For complex integrated circuit design, circuit functions need to be completed through multiple levels of description.

Digital circuit design classification: system level, architecture level, register transfer level (RTL), gate level and transistor level, etc. The so-called level includes two meanings, one is the designer's understanding of the circuit, and the other is the description method allowed.

Related analysis:

The task of system-level design is mainly to define the function and external characteristics of the circuit. The designer only needs to divide the circuit into several abstract functional modules and clearly define the logical functions of each functional module.

The architecture-level design should be more specific. At this level, the circuit should be described as several typical logical components connected to each other and a state machine that controls its data transmission. Typical logic components include counters, registers, arithmetic operation units, etc., also known as data paths (Data path), the state machine is a special part of the design, it controls the work of the data channel. In the above two descriptions, there is no limit to the description method, just make the problem clear.

The description of the register transfer level is the most important description in ASIC design and must be completed using a hardware description language. The so-called register transfer level description is based on the realization that any digital circuit, regardless of its function, is implemented by a combinational logic circuit between registers and registers. Registers are used to store data, and combinational circuits are used to transfer data. The RTL code must ensure synthesizability, and only part of the description statements in the hardware description language can be used. The structure of the circuit should be vaguely visible from the RTL code, but not too specific. It is not good to refine the code to logic gates and triggers, because the conversion from RTL description to cell is the task of logic synthesis tools. Writing to the cell level artificially not only reduces the readability of the code, but also is not conducive to optimization.

In ASIC design, gate-level and transistor-level circuits are generated by EDA tools, and the designer's task is to give correct RTL-level code.