Map is a step in the implementation process of Xilinx devices. In particular, in the mapping step, the logic in the netlist (if the input netlist is from a schematic tool) is optimized to Xilinx device resources (such as LUTs, registers, tri-state buffers, etc.). Then pack LUT, register, etc. into slice and IOB.
FPGA Spartan-XL Family 10K Gates 466 Cells 217MHz 3.3V 144-Pin TQFP
Xilinx BGA
CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 200MHz 0.18um, CMOS Technology 1.8V 44-Pin VQFP
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 324-Pin FBGA
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 256-Pin FTBGA
Support
