DDR memory uses the SSTL2 standard that supports 2.5V voltage. For older SDRAM memories, it supports the 3.3V LVTTL standard.
Commonly used level standards are TTL, CMOS, LVTTL, LVCMOS, ECL, PECL, LVPECL, RS232, RS485, etc., as well as some relatively high speed LVDS, GTL, PGTL, CML, HSTL, SSTL, etc.
TTL: Transistor-Transistor Logic transistor structure.
Vcc: 5V; VOH>=2.4V; VOL<=0.5V; VIH>=2V; VIL<=0.8V.
Because there is still a lot of idle between 2.4V and 5V, it is not good for improving the noise margin, it will increase the system power consumption in vain, and it will affect the speed. So later, a part of it was cut off. That is the LVTTL behind.
LVTTL is divided into 3.3V, 2.5V and lower voltage LVTTL (Low Voltage TTL).
3.3V LVTTL: Vcc: 3.3V; VOH>=2.4V; VOL<=0.4V; VIH>=2V; VIL<=0.8V.
2.5V LVTTL: Vcc: 2.5V; VOH>=2.0V; VOL<=0.2V; VIH>=1.7V; VIL<=0.7V.
The lower LVTTL is not commonly used and will not be discussed first. It is mostly used in high-speed chips such as processors, so check the chip manual when using it.
The overshoot of TTL level is generally more serious. It may be a 22 ohm or 33 ohm resistor at the beginning. When the TTL level input pin is floating, it is internally considered to be a high level. If you want to pull down, apply a pull-down below 1k. TTL output cannot drive CMOS input.
CMOS: Complementary Metal Oxide Semiconductor PMOS+NMOS.
Vcc: 5V; VOH>=4.45V; VOL<=0.5V; VIH>=3.5V; VIL<=1.5V.
Compared with TTL, there is a larger noise margin, and the input impedance is much larger than the TTL input impedance. Corresponding to 3.3V LVTTL, LVCMOS appeared, which can directly drive each other with 3.3V LVTTL.
3.3V LVCMOS: Vcc: 3.3V; VOH>=3.2V; VOL<=0.1V; VIH>=2.0V; VIL<=0.7V. (VIH refers to the voltage value at which the input gate is high level, and VIL refers to the voltage value at which the output gate is low level)
2.5V LVCMOS: Vcc: 2.5V; VOH>=2V; VOL<=0.1V; VIH>=1.7V; VIL<=0.7V.
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