LVPECL is Low Voltage Positive Emitter-Couple Logic, which is low voltage positive emitter coupling logic. It uses 3.3V or 2.5V power supply. LVPECL is evolved from PECL. PECL is Positive Emitter-Couple Logic, which is positive emitter coupling logic. Meaning, using 5.0V power supply, and PECL is evolved from ECL, ECL is Emitter-Couple Logic, which is the emitter coupling logic, ECL has two supply voltages VCC and VEE. When VEE is grounded and VCC is connected to a positive voltage, the logic at this time is called PECL; when VCC is grounded and VEE is connected to a negative voltage, the logic at this time becomes NECL, and VEE is generally connected to a -5.2V power supply; the general narrow sense of ECL is Refers to NECL.
1. The output impedance is low 6~8ohm), the output impedance is high (can be regarded as infinity), so the driving ability is particularly strong, it can drive the transmission line of 50~130ohm characteristic impedance and the AC characteristics have not changed significantly. Because of its strong driving capability, it supports transmission over longer distances, so backplane wiring or long cable transmission basically uses ECL logic.
2. ECL devices are less sensitive to changes in voltage and temperature than TTL and CMOS devices. The clocks generated by the ECL clock driver have better concurrency and smaller skew.
3. Compared with LVDS, which is also a differential signal, ECL supports a higher rate. Due to process limitations, VDS logic rarely has applications higher than 1.5GHz, and ECL can be applied in situations higher than 10GHz. It can be said that high At 5GHz, it is basically the world of ECL and CML. Among all digital circuits, ECL has the highest working speed, and its delay is less than 1ns. It is used in small and medium-sized integrated circuits, high-speed, ultra-high-speed digital systems and equipment.
4. Wider adaptability to transmission line impedance. LVDS is a current type drive, and its 100ohm matching resistor at the terminal also has the function of generating voltage. Therefore, in order not to change the swing of the signal, the resistance of the termination resistor must be 100 ohm. In order to ensure better signal integrity, the impedance of the transmission line of the VDS must also be accurately controlled at 50 ohm, otherwise S1 problems such as reflection are likely to occur.
Like its advantages, the disadvantages of ECL are also obvious, that is, large power consumption, small noise tolerance, and weak anti-interference ability.
The logic swing of the ECL circuit is only 0.8V, and the DC noise tolerance is only 200mV. It can be said that the high-speed performance of ECL comes at the cost of high power consumption and low noise tolerance.
The standard output load of PECL is 50ohm to VCC-2V. Under this load condition, OUT+ and OUT- The typical value of the static level is VCc-1.3V, and the output current of OUT+ and OUT- is 14mA.
PECL output circuit structure:
The input of PECL is a differential pair with high input impedance. The common-mode voltage of the differential pair needs to be biased to VCC-1.3V, which allows the maximum dynamic input signal level. Some chips have integrated a bias circuit inside, and can be directly connected when used, and some chips are not added, and a DC bias needs to be added outside the chip when used.
PECL input circuit structure:
FPGA Spartan-IIE Family 600K Gates 15552 Cells 357MHz 0.15um Technology 1.8V 676-Pin FBGA
FPGA Spartan-3E Family 500K Gates 10476 Cells 657MHz 90nm Technology 1.2V 320-Pin FBGA
CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 200MHz 0.18um, CMOS Technology 1.8V 44-Pin VQFP
CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 125MHz 0.18um Technology 1.8V 256-Pin FTBGA