I/O

Interface function

Due to the wide variety of computer peripheral devices, almost all of them use electromechanical transmission equipment. Therefore, the CPU has the following problems when exchanging data with I/O devices:

Speed mismatch: The working speed of I/O devices is much slower than that of the CPU, and due to different types, the speed difference between them is also very large. For example, the transmission speed of the hard disk is much faster than the printer.

Timing mismatch: Each I/O device has its own timing control circuit, which transmits data at its own speed and cannot be unified with the timing of the CPU.

Information format does not match: different I/O devices store and process information in different formats, for example, they can be divided into serial and parallel; they can also be divided into binary format, ASCII encoding, and BCD encoding.

Information types do not match: different I/O devices use different signal types, some are digital signals, and some are analog signals, so the processing methods used are also different.

Based on the above reasons, the data exchange between the CPU and peripherals must be completed through the interface, usually the interface has the following functions:

(1) Set the data registration and buffer logic to adapt to the speed difference between the CPU and peripherals. The interface is usually composed of some registers or RAM chips. If the chip is large enough, batch data transmission can be achieved;

(2) Capable of converting information format, such as serial and parallel conversion;

(3) Ability to coordinate the differences in types and levels of information between the CPU and peripherals, such as level conversion drivers, digital-to-analog or analog-to-digital converters, etc.;

(4) Coordinate timing differences;

(5) Address decoding and device selection functions;

(6) Set up interrupt and DMA control logic to ensure that interrupt and DMA request signals are generated under the condition of interrupt and DMA permission, and complete interrupt processing and DMA transfer after receiving the interrupt and DMA response.

Way to control

There are several ways for the CPU to control peripherals through the interface:

(1) Program query method

In this way, the CPU inquires about the current status of the specified peripheral through the I/O instruction. If the peripheral is ready, it will input or output the data, otherwise the CPU will wait and loop the query.

The advantage of this method is that the structure is simple, and only a small amount of hardware circuit is needed. The disadvantage is that because the speed of the CPU is much higher than that of the peripherals, it is usually in a waiting state and the working efficiency is very low.

(2) Interrupt processing method

In this way, the CPU no longer passively waits, but can execute other programs. Once the peripheral is ready for data exchange, it can make a service request to the CPU. If the CPU responds to the request, it temporarily stops the execution of the current program. To execute the service program corresponding to the request, after completion, continue to execute the originally interrupted program.

The advantages of the interrupt handling method are obvious. It not only saves the CPU the time it takes to query the status of the peripherals and wait for the peripherals to be ready, improves the CPU's working efficiency, and also meets the real-time requirements of the peripherals. But each I/O device needs to be assigned an interrupt request number and corresponding interrupt service program. In addition, an interrupt controller (I/O interface chip) is needed to manage the interrupt requests made by the I/O device, such as setting an interrupt mask, Interrupt request priority, etc.

In addition, the shortcoming of the interrupt processing method is that every time a character is transmitted, an interrupt is started, the interrupt controller is started, and the scene must be retained and restored to continue the execution of the original program. It takes a lot of work, so if a large amount of data exchange is required, The performance of the system will be very low.

(3) DMA (direct memory access) transfer method

One of the most obvious characteristics of DMA is that it does not use software but uses a special controller to control the data exchange between memory and peripherals without CPU intervention, which greatly improves the work efficiency of CPU.

Before DMA data transfer, the DMA controller will apply to the CPU for bus control. If the CPU allows it, it will hand over the control. Therefore, during data exchange, the bus control is controlled by the DMA controller. After the transfer is completed, The DMA controller returns the bus control to the CPU.

(4) Channel mode

I/O device failure

The failure performance of I/O devices in the computer mainly has the following three aspects:

I/O devices can't be used normally, including various external interfaces, the keyboard of the notebook can't type, and the touch screen is not working.

Computer maintenance tools: When the motherboard diagnostic card is inserted into the motherboard to run the code, it will display the FF code, 00 code, DD code or no code, and the phenomenon of repeatedly running C1~C5 code.

Failures such as short circuiting of I/O devices may also cause the computer to be impacted or disturbed by static electricity when connected to external devices, which may damage other capacitors, diodes and other components. As a result, there is a serious consequence that the device cannot be turned on.

Preventing I/O equipment failure: I/O equipment is a sophisticated electronic product. It has strict requirements on the environment during use. Do not use it in a high temperature and humid environment.

CPU bottleneck on i/o process

In a mainframe environment with limited CPU performance, i/o processes can affect the workload.

　　On systems with limited CPUs, batch processing can make i/o performance worse. Usually in the case of the lowest system priority, when the CPU is bottleneck, the batch process barely runs i/o because it has to compete for resources with the online process. Every time i/o, a process starts to release CPU resources and is taken over by a higher priority process. But even if the i/o process is completed quickly, the batch process also needs to compete for the process resources of the completed task and accept CPU thread scheduling.

　　 Online processes usually get the necessary CPU resources. The i/o process will not slow down the workload of the customer information control system (CICS) or information management system (IMS) because each i/o is not synchronized.

　　However, some special processes are affected by CPU bottlenecks like batch processing. In CICS, once the transaction processing completed by i/o, before i/o continues to work, i/o has passed the CICS chain scheduler. It is especially obvious in CICS workloads that i/o has deep scheduling queues.

　　 The IMS transaction running message processing area (MPR’S) takes a different path, but all are the same. Once the database i/o is completed, IMS will notify the MPR that is competing with the server for resources before it can process more work.

　　 The fastest i/o cannot be achieved. Therefore, use data input memory as much as possible to prevent bottlenecks in a CPU-limited environment. The data in i/o input memory includes buffer pool, reference table, data cache space and other methods.