An early and still common form of ASIC chip. This requires the use of bespoke masks for the last few stages of chip fabrication to be tailored to a specific design.
The gate array is a semi-custom integrated circuit, which can be divided into two kinds of channel and no channel. A channel gate array is to arrange the gates into an array form on a chip, strictly speaking, to arrange the cells (containing several devices) into an array form. Menhai Technology does not implement a certain routing channel area, and the connection between macro cells will be carried out on the useless effective device area.
The gate array refers to a semi-customized chip prepared by a semiconductor manufacturer that has formed a logic gate called a basic unit on a silicon wafer, and by wiring according to a user's desired circuit, forming a circuit on the motherboard. The gate array uses a general-purpose motherboard, which not only can greatly shorten the production period, but also can achieve low cost, so it is widely used in a variety of industrial equipment such as digital cameras, DVD recorders and other civilian equipment to robots, industrial machine tools and other industrial equipment field.
The gate array is a semi-custom integrated circuit, which can be divided into two kinds of channel and no channel.
A channel gate array is to arrange the gates into an array form on a chip, strictly speaking, to arrange the cells (containing several devices) into an array form. The cells are arranged in rows, and there is a channel area for connection between the rows, and the width of the channel is fixed. This is where the name "channel gate array" comes from. In order to ensure that the wiring between the cells has a 100% wiring rate, a wider channel is required, but this will result in useless routing areas, thus wasting silicon area.
In order not to waste a lot of silicon area and overcome the shortcomings of the low gate utilization rate of conventional gate arrays, the concept of Menhai was proposed in 1982, that is, a channelless gate array. Menhai Technology does not implement a certain routing channel area, and the connection between macro cells will be carried out on the useless effective device area. Menhai Technology has increased the integration density of circuits, and can integrate more than 100,000 gates on a single die. At the end of the 20th century, 500,000 to 700,000 gate circuits with a gate delay of 0.4 ns could be designed on a single chip.
Xilinx BGA
FPGA Spartan-XL Family 5K Gates 238 Cells 250MHz 3.3V 100-Pin VTQFP
CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 323MHz 0.18um, CMOS Technology 1.8V 56-Pin CSBGA
CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 323MHz 0.18um, CMOS Technology 1.8V 32-Pin QFN
CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 200MHz 0.18um, CMOS Technology 1.8V 56-Pin CSBGA
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