Synopsys' FPGA design tool has now been replaced by Synplify.
Keywords: Foundation, FPGA, Express, latch, invert, 4000, Spartan, 4000XL, SpartanXL
FPGA Express 3.x incorrectly inverts all load (G input) signals for inferred ILD latches.
This happens when targeting all FPGA devices except for Virtex. When examining the XNF file you
will see a ", INV" on the G pin of the ILD component.
Several workarounds are available:
- Instantiate the ILD component
- Invert the Gate signal before latches that are moved into the IOB
- Disable the I/O Register Merge feature in the Express Constraints Editor
- Use registers instead of latches
FPGA Spartan-XL Family 5K Gates 238 Cells 217MHz 3.3V 84-Pin PLCC
FPGA Spartan Family 10K Gates 466 Cells 166MHz 5V 144-Pin TQFP EP
CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 323MHz 0.18um, CMOS Technology 1.8V 44-Pin PLCC
CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 323MHz 0.18um, CMOS Technology 1.8V 44-Pin VQFP