Synopsys' FPGA design tool.
Design input includes three ways of using hardware description language HDL, state diagram and schematic diagram input. The HDL design method is a good form for designing large-scale digital integrated circuits. In addition to the two forms of VHDL and Verilog HDL in the IEEE standard, there are also dedicated languages introduced by respective FPGA manufacturers, such as AHDL under Quartus. HDL language description is strong in state machine, control logic, and bus functions, so that the circuit described can be better implemented with specific hardware units under the action of a specific synthesizer (such as Synopsys' FPGA Compiler II or FPGA Express); and the principle Picture input has the characteristics of strong graphics, thrifty units, and clear functions in top-level design, data path logic, and manual optimization circuits. In addition, in the Altera Quartus software environment, you can use the Momory Editor to directly edit the internal memory. Into the data. The common method is based on HDL language, supplemented by schematic diagram, and mixed design to give play to their respective characteristics.
Generally, FPGA vendor software has an interface with third-party software, and third-party design files can be imported for processing. For example, both Quartus and Foundation can use the EDIF netlist as the input netlist for direct placement and routing. After placement and routing, the generated files can be handed over to a third party for subsequent processing.
Field Programmable Gate Array
CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 323MHz 0.18um, CMOS Technology 1.8V 56-Pin CSBGA
CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 323MHz 0.18um, CMOS Technology 1.8V 44-Pin VQFP