EDIF is the English acronym for Electronic Design Interchange Format. EDIF integrates the best features of multiple formats. The EDIF100 version in 1985 provides a format for exchanging information for gate arrays, semiconductor integrated circuit design and wiring automation, and the EDIF200 version is the standard format for exchanging design data between different EDA manufacturers. .
EDIF is the English acronym for Electronic Design Interchange Format. EDIF integrates the best features of multiple formats. The EDIF100 version in 1985 provides a format for exchanging information for gate arrays, semiconductor integrated circuit design and wiring automation, and the EDIF200 version is the standard format for exchanging design data between different EDA manufacturers. . The CAD framework standard solves the problem of tool integration and real-time communication of different EDA manufacturers. The EDIF format solves the data communication problem of design completed with tools of different EDA manufacturers.
The overall structure of the EDIF file is as follows:
of
(edif name
(status information)
(design where-to-find-them)
(external reference-libraries)
(library name
(technology defaults)
(cell name
(viewmap map)
(view type name
(interface external)
(contents internal)
Visible from this structure: the EDIF file contains a series of libraries (libraries), each library contains a series of cells (cells), each cell has one or more views (views).
Views are described in formats such as schematic, layout, behaviour, and document. Each view has an interface (interface) and a content (contents), through them to clearly define the view. The Cell unit is also connected to other View views through the (view map) attribute.
To LPM (Library of Parameterized Modules), we must talk about EDIF (Electronic Design Interchange Format). The EDIF file is a file format for transferring design information between EDA vendors and EDA vendors and IC vendors. LPM originally appeared as an attachment to the EDIF standard.
Standardization process of EDIF and LPM:
In 1988, ANSI/EIA-548: Electronic Design Interchange Format (EDIF), Version 2.0.0.
In 1990, the LPM standard was proposed for EIA review.
In 1993, EIA 618: Electronic Design Interchange Format (EDIF) Version 3 0 0 Level 0 Reference Manual, LPM as an attachment to the EDIF standard, became a transition standard for EIA.
In 1995, EIA PN 3714: Library of Parameterized Modules (LPM) Version 201.
In 1996, EIA-682: EDIF Version 400 (EIA-682-96) Electronic Design Interchange Format.
In 1999, EIA/IS-103A: Library of Parameterized Modules (LPM) Version 2.0.
From the chronological point of view, the period from 88 to 90 happened to be a period when the semi-custom design style surpassed the full custom design style and became the mainstream of VLSI chip design. The LPM standard may have responded to the needs of semi-custom design.
EDIF files are the standard format for transferring information between EDA tools. Friends who have drawn circuit schematics and PCBs must know that after the schematic files are drawn, they need to "generate a netlist". Before PCB layout and wiring, they must first "introduce a netlist" so that the relationship between the schematic file and the PCB file can be established. "Logical mapping relationship". EDIF file is a format of netlist file. In many cases, there is a one-to-one correspondence between the module graphics in the schematic file and the “package” in the PCB file. This “physical mapping relationship” is established through the “library file”. The "library file" contains the name and graphics of the schematic module, as well as the name and graphics of the package file. In this way, the "physical mapping relationship" is established. Between different EDA tools, such as Protel, Cadence and PowerPCB, the logical mapping relationship is easy to be common to each other, but due to the support of different "library files", the physical mapping relationship is often not established.
In the field of IC design (including PLD design), EDIF files encounter similar problems: synthesis tools and implementation tools must agree. Before the LPM standard was proposed, this was difficult to achieve. After all, there are too many implementation processes and EDA tools in the field of IC design.
Before the LPM standard was proposed, there was no unified standard for the description of certain logics, and the description methods were all process dependent (Technology dependent), so the EDIF file generated by the comprehensive tool was not portable. After adopting the LPM standard, for the logic contained in the LPM library, all synthesis tools use the same behavior description method to generate the same EDIF file to achieve the correct mapping of design inputs and netlists; the implementation tools include their respective process libraries and The unique mapping relationship between the LPM libraries, so as to be able to "read" the EDIF file containing the LPM description, and realize the correct mapping between the netlist and the process implementation. In this way, the transplantation of EDIF files between different implementation tools is not a problem. (LPM is not the only solution. For example, current EDA tools often support each other’s specific library files and netlist formats, especially professional EDA companies like Synplicity, and support many companies’ devices and netlist formats and macro cells. ; And Altera and Xinlinx cannot support each other)
The principle embodied in this process is that by adding a mapping level, one mapping relationship is transformed into two mapping relationships, and the intermediary of the two mapping relationships—the EDIF file containing the LPM description—has portability.
FPGA Spartan-IIE Family 50K Gates 1728 Cells 400MHz 0.15um Technology 1.8V 256-Pin FTBGA
FPGA Spartan-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 256-Pin FTBGA
Xilinx PLCC
Field Programmable Gate Array
Xilinx BGA
Support
