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A
Algorithm module
AlexNet
ABEL
ADC
AGP
ASSP
ATPG
ALU
APR
ARM
ASM
ASDO
ATE
ACE
arduino
ASIC
B
Bitgen
BGA
BIST
bitstream
block SelectRAM
BLVDS
BSDL
BSCAN
BUFGMUX
BUFT
BCD
BIDI
BSP
BST
BUFGCE
BRAM
C
Certify
core
Cadence Allegro
Crossbar
carry logic
ChipScope ILA
CMOS
combinatorial
compile
configuration
CORE Generator system
CPU
CS
CTT
Combinatorial logicdd
Cache
CAD
CAE
CAM
CAT
CCCS
CCVS
CCD
CIMS
CISC
CLCC
CQFP
CSL
CONF_DONE
CLKUSR
CRC_ERROR
CLB
CPLD
D
D flip-flop
DAC
daisy chain
DCI
DDR
Design Manager
die
DFT
DLL
DSM
DCC
DC-DC
DF
DFF
DIP
DEV_CLRn
DEV_OE
DCLK
DATA0
DMA
DSP
DCM
DDR3
DRAM
DDS
E
EA
ECO
EDIF
EAB
EPF
EPLD
EPIC
EBR
EPROM
EEPROM
EDA
F
FPGA Express
FPGA Compiler Ⅱ
FG
FIFO
flash memory
Flow Engine
Foundation
footprint
function generator
Flip-Flop
Firm Core
FFT
FIR
FPSC
FIQ
FLEX
FPLA
FSK
Foundry
FSM
FPGA
G
GNDD_PLL
GNDA_PLL
Gate Array
GDSll
global clock buffer
gray code
GSR
GTL
GTS
GUI
GMII
GAL
GDF
GLB
GPIO
GRP
Global Buffers
H
HD
HDL
HLS
HSTL
HP
HR
Hard Core
HDPLD
HEX
High-Level Language
HDMI
I
Interconnect
IBM
IBIS
IC
ICE
instantiate
Intellectual Property
IO
I/O
IP
ISE
IP core
IEEE
IOE
INIT_DONE
IIR
IIS
IRQ
ISR
ispGAL
ispGDS
ispLSI
Interrupt Vector Table
IO blocks
IO pads
IBUF
ISERDES
IOB
J
JEDEC
JKFF
JLCC
JPEG
JTAG
K
KINTEX7
L
LVCMOS
latency
Leonardo Spectrum
Libero
LAB
Levels of Abstraction
Latch
Logic Analyzer
LC
LE
LMF
LSC
LPM
LSIC
LS
LVDS
LOC
LFSR
Libraries Guide
LM
LogiBLOX
LVPECL
LVTTL
LUT
LCA
labview
M
Multiplier
MP
MPSoC
MGT
MSEL
MMCM
MAC
Macrocells
MAX
MMU
MMIO
MOSFET
MPLD
MPU
macro
MPEG
MQFP
MSI
map
MHZ
Modelsim
Matlab
MIPI
N
NGDBuild
nCNFIG
nW
NJF
NoC
nCEO
nCONFIG
nCE
nCSO
nSTATUS
NIOPULLUP
NCD
Netlist
NMOS
NCF
NRE
Nios II
O
OpenVINO
OTG
Oscilloscope
OE
OLMC
OP
ORCA
ORP
OTP
OFFSET IN
OFFSET OUT
one-hot
optimize
P
period
PROSEL
Primitive
Pad-to-pad delay
Place & route
Primitives
PDIP
Pin locking
PCIe
PC
PCB
PGA
PIE
PIP
PLSI
PMOS
POF
PQFP
PTSA
pad-to-pad
PAL
P&R
PAR
PCI
pipeline
PECL
PLA
Place and Route
pipelining
PLD
PLL
PRBS generator
PRBS
Project Navigator
priority encoded
PROM
PLCC
PWM
Q
Qsys
QFP
Quartus
R
RS-232
RGMII
RLOC
Register
RISC
RTOS
RAM
regression
RPM
RTL
RISC-V
S
SPLD
spartan
SelectIO
SoC
Sequential logic
SGMII
Skew
SCH
SP
SPICE
SDRAM
SSI
SWI
SYM
SC
scan
SDF
Selectl/O
SelectRAM
SelectROM
Silicon
simulation
simprims
slices
SRAM
SRL
SSTL
ST
stamp
startup
STA
synchronous
Slice
Synplify
Sobel
SRIO
SOPC
Simulink
SPI
T
TEMPDIODEN
TTM
TOP_DOWN
TRACE
TAP
TQFP
TT
TI
timing constraints
translate
TTL
TWR
Testbench
U
uP
UltraScale
UDP
UCF
UART
UIM
um
UI
Unisim
V
Vitis
VCCSEL
VCCA_PLL
VCCA
VCCD
VCC
VCCAUX_IO
VCCPD
VCCAUX
VREF
VSSD
VSSA
VCCINT
VCCO
VCCIO
VCCS/VCVS
VHSIC
VLSI
vhdl
version
VITAL
Vivado
Verilog
W
Watchdog Timer
X
XACT
XC
XDE
XDM
XNF
XST
XADC
Z
ZPUino
zynq
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