Flip-Flops

In the preceding examples, the gates are arranged so that you will always get the same outputs for a given set of input values. If you start feeding back the outputs of logic gates to an earlier gate that affects the first gate’s inputs, then you can give your network of logic gates the ability to remember things. This kind of logic is called sequential logic.

One of the fun things about electronics is that it is a relatively modern field, and its pioneers could ditch the Latin pomposity of earlier naming conventions and call things that flip and flop from one state to another a flip-flop. For those with a yearning to call them something less interesting, you may also refer to them as bistables.

Set-Reset Flip-Flop

Take a look at the schematic of Figure 1-10. This is called a set-reset (SR) flip-flop. Having introduced the idea that high means 1 and low means 0, let’s stick to numbers for logic values. Imagine that initially S (set) is 1 and R (reset) is 0. Because one input (S) to NOR gate A is 1, then it doesn’t matter about the other input to NOR gate A, the output will be 0. This 0 output from NOR gate A means that the top input to NOR gate B will also be 0. The other input to NOR gate B (R) is also 0, so the output of NOR gate B will be 1, making the lower input to NOR gate A also 1. Next, imagine that you now set S to 0. This will have no effect on the output of NOR gate A.

Having set the output Q to 1 by setting S to 1, Q will not change whatever we do with S: it will change only if R is set to 1, making the output of NOR gate B (Q) 0. The output of NOR gate A is labeled as Q with a line over it. The line (called a bar) indicates that the output is inverted, and Q– will always be the inverse of Q.

Programming FPGAs: Getting Started with Verilog

A set-reset flip-floppng

The SR flip-flop just described is used occasionally, but perhaps the most commonly used and flexible type of flip-flop is the D flip-flop. This can be made from a load of NAND or NOR gates, but you only ever need to use it as a logical block in its own right. Figure 1-11 shows the schematic symbol for a D flip-flop.

A D flip-floppng

The D flip-flop still has the S, R, Q, and Q–, but it has two extra pins D and CK (clock). The clock symbol is often shown as a little triangular notch. You can still use S and R to set and reset the flip-flop, but you are more likely to use D and CK.

The concept of a clock is something that is essential to digital electronics. It synchronizes the system so that the slight delays caused by logic gates changing from high to low and propagated through multiple paths between each other do not cause glitches if the outputs haven’t finished settling. A clock generally will be connected to a signal that flips back and forth between high and low. FPGAs have a built-in clock signal that you will use in most of the examples in this book. This signal is 12 to 50 MHz depending on which of this book’s example FPGA boards you are using. This is 12 to 50 million cycles of high/low per second.

When the clock signal goes high, whatever value of D (0 or 1) will be latched into the output Q. This may not sound very exciting, but it does allow you to construct the much-used shift registers and counters described in the following sections.

TABLE OF CONTENTS

Set-Reset Flip-Flop