Mixed Domain Modeling in Verilog-AMS

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In Verilog-AMS, there is a “Disciplines” package that defines all the standard technologies and their basic natures. This is usually implemented in a single Verilog-AMS code disciplines.vams which must be included in the header of models using Verilog-AMS and these disciplines.

The implication is that these natures are all intrinsically real types, but the nature definition will set up the name, units, tolerances, and related natures. For example, the nature for Voltage could be defined as follows:

1 / Potential in volts

2 nature Voltage

3 units = "V";

4 access = V;

5 idt_nature = Flux;

6 ‘ifdef VOLTAGE_ABSTOL

7 abstol = ‘VOLTAGE_ABSTOL;

8 ‘else

9 abstol = 1e−6;

10 ‘endif

11 endnature

With each nature defined, then a complete discipline can then be implemented with the through and across variables defined.

1 discipline electrical

2 potential Voltage;

3 flow Current;

4 enddiscipline

Note that in Verilog-AMS, the “across” variable is called “potential” and the “through”variable is referred to as the “flow.”

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Mixed Domain Modeling in Verilog-AMS