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Consider a simple comparator that has two electrical inputs (p and m), an electrical ground (gnd) and a digital output (d). The comparator has a digital output of 1 when p is greater than m and 0 otherwise (Figure 18.5).
The entity defines the terminals (p, m, gnd), digital output (d), input hysteresis (hys), and the propagation delay (td).
propagation delay (td).
1 use ieee.electrical_system.all; 2 use ieee.std_logic_1164.all; 3 entity comparator is
4 generic ( 5 td : time := 10 ns;
6 hys : real := 1.0e−6;
7 );
8 port ( 9 d : out std_logic := ’0’;
10 terminal p,m,gnd : electrical
11 );
12 end entity comparator;
The first step in the architecture is to define the input voltage and basic process structure:
1 architecture simple of comparator is
2 quantity vin across p to m;
3 begin
4 p1 : process
5 constant vh : real := abs(hys)/2.0;
6 constant vl : real := −abs(hys)/2.0;
7 begin
8 −− The comparator digital handler goes here
9 wait on vin’above(vh), vin’above(vl);
10 end process;
11 end architecture simple;
The quantity vin is defined as the voltage across the input pins p and m.
1 quantity vin across p to m;
Notice that no current is defined (i.e., assumed to be zero) so there is no input current to the comparator. Also notice that there is no input voltage offset defined; this could be added as a refinement to the model later. The process defines the upper and lower thresholds (vh and vl) based on the hysteresis:
1 constant vh : real := abs(hys)/2.0;
2 constant vl : real := −abs(hys)/2.0;
The process then defines a wait statement, checking vin for crossing either of those threshold values:
wait on vin’above(vh), vin’above(vl);
The final part of the process is to add the digital output logic state dependent on the threshold status of vin:
1 if vin’above(vh) then
2 d <= ’1’ after td;
3 elsif not vin’above(vl) then
4 d <= ’0’ after td;
5 end if;
The output state (d) is then scheduled after the delay time defined by td.
The completed architecture is shown as follows:
he completed architecture is shown as follows:
1 architecture simple of comparator is
2 quantity vin across p to m;
3 begin
4 p1 : process
5 constant vh : real := ABS(hys)/2.0;
6 constant vl : real := −ABS(hys)/2.0;
7 begin
8 if vinabove(vh) then
9 d <= ’1’ after td;
10 elsif not vinabove(vl) then
11 d <= ’0’ after td;
12 end if;
13 wait on vin’above(vh), vin’above(vl);
14 end process;
15 end architecture simple;
Manufacturer:Xilinx
Product Categories: FPGAs
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Manufacturer:Xilinx
Product Categories: FPGAs
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
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