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A Basic Switch Model

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A Basic Switch Model

Consider a simple digitally controlled switch that has the following characteristics:

1. Digital control input (d)

2. Two electrical terminals (p and m)

3. On resistance (Ron)

4. Off resistance (Roff)

5. Turn on time (Ton)

6. Turn off time (Toff)

Using this simple outline a basic switch model can be created in VHDL-AMS. The entity is given here: 

1 use ieee.electrical_system.all; 

2 use ieee.std_logic_1164.all; 

3 entity switch is


4 generic ( ron : real := 0.1; −− on resistance

5 roff : real := 1.0e6; −− off resistance

6 ton : real := 1.0e−6; −− turn on time

7 toff : real := 1.0e−6); −− turn off time

8 port ( 9 d : in std_logic;

10 terminal p,m : electrical);

11 end entity switch;

The basic structure of the architecture requires that the voltage and current across the terminals of the switch be dependent on the effective resistance of the switch (reff):


1 architecture simple of switch is

2 quantity v across i through p to m;

3 quantity reff : real;

4 signal r_eff : real := roff;

5 begin

6 process (d)

7 begin

8 −− the body of the behavior goes here

9 end;

10

11 i = v / reff;

12 end;

The process waits for changes on the input digital signal (d) and schedules a signal r_eff to take the value of the effective resistance (ron or roff) depending on the logic value of the input signal. The VHDL for this functionality is shown here:

1 process (d)

2 begin

3 if ( d = ’1’ ) then

4 r_eff <= ron;

5 else

6 r_eff <= roff;

7 end if; 

8 end;

When the signal r_eff changes, then this must be linked to the analog quantity reff using the ramp function. Previously we showed how the ramp could define a risetime, but in fact it can also define a falltime. Implementing this in the switch model architecture, we get the following VHDL-AMS:


 reff == r_eff’ramp ( ton, toff );

2 i == v / reff;

The complete VHDL-AMS model for the switch architecture is given as:1 architecture simple of switch is

2 quantity v across i through p to m;

3 quantity reff : real;

4 signal r_eff : real := roff;

5 begin

6 process (d)

7 begin

8 if (d=1) then



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