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Differential Equations in VHDL-AMS
VHDL-AMS also allows the modeling of linear differential equations using the two differential operators:
• ’dot (Differentiate the variable with respect to time);
• ’integ (Integrate the variable with respect to time).
We can illustrate this by taking two examples, a capacitor and an inductor. First consider the basic equation of a capacitor:
Using a similar model structure as the resistor, we can define a model entity and architecture,
but what about the equation? In VHDL-AMS, the ’dot operator is used on the voltage to
represent the differentiation as follows:
i == c∗v’dot;
Therefore, a complete capacitor model in VHDL-AMS could be implemented as follows:
1 library ieee;
2 use ieee.electrical_systems.all; 3 entity capacitor is
4 generic( 5 cap : real := 1.0e−9);
6 port( 7 terminal p : electrical;
8 terminal m : electrical
9 );
10 end entity;
11
12 architecture simple of capacitor is
13 quantity v across i through p to m;
14 begin
15 i == cap ∗ v’dot;
16 end architecture simple;
What about an inductor? The basic equation for an inductor is given as:
which could also be written as:
Obviously, the most direct way to implement this equation would be to use the ’integ operator; however, care should be taken with the integration operator as some simulators do not handle the integration function in the same manner (in fact, some simulators do not support it at all well). Obviously the initial condition must be considered and in addition different implementations can occur across simulators. One standard approach is to use what is called implicit integration, whereby, using the differential equation, the integral function can be inferred. However, the resulting implementation in its simplest form could be as follows:
1 library ieee;
2 use ieee.electrical_systems.all; 3 entity inductor is
4 generic( 5 ind : real := 1.0e−9);
6 port( 7 terminal p : electrical;
8 terminal m : electrical
9 );
10 end entity;
11
12 architecture simple of inductor is
13 quantity v across i through p to m;
14 begin
15 i == (1.0/ind) ∗ v’integ;
16 end architecture simp
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