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As before, the model (in this case a Verilog module) can now be put together and is shown here. Notice that for RTL we require both a clock and a reset.
re. Notice that for RTL we require both a clock and a reset.
1 module cross_product (
2 clk, / clock
3 rst, / reset
4 a, / number a
5 b, / number b,
6 result / result of the product
7 );
89 input clk;
10 input rst;
11
12 input signed [7:0] a;
13 input signed [7:0] b;
14
15 output reg [15:0] result;
16
17 reg [2:0] i;
18
19 always @ (posedge clk)
20 begin
21 if (rst = 1 ) then
22 i = 3b’000;
23 else
24 i = i + 1;
25 end if
26 accumulator <= sum;
27
28 if (i=0) then
29 addin <= 0;
30 else
31 addin <= accumulator;
32 end if
33 end
34
35 ai <= a[i];
36 bi <= b[i];
37 multiply <= ai ∗ bi;
38 result <= accumulator;
39
40 endmodule
Again, even with Verilog which generally has a little simpler syntax than VHDL, in this simple model it is difficult to extract the key behavior of the state machine. In a complex controller it verges on the impossible unless the structure is well known and understood, which is an important lesson when using any kind of synthesis tool using VHDL or Verilog at any level.
Now reconsider using behavioral code instead. The model uses the same packages and libraries as the RTL model; however, notice that there is no need for an explicit clock or reset.
1 module cross_product (
2 a, / number a
3 b, / number b,
4 result / result of the product
5 );
67 input clk;
8 input rst;
9
10 input signed [7:0] a;
11 input signed [7:0] b;
12
13 output reg [15:0] result;
14
15 reg [2:0] i;
16
17 always @ (a or b)
18 begin
19 for (i = 0; i < 8; i = i +1) begin
20 begin
21 ai <= a[i];
22 bi <= b[i];
23 accumulator <= accumulator + ai ∗ bi;
24 end
25 end
26
27 result <= accumulator;
28
29 endmodule
Notice that it is much easier to observe the functionality of the model and also the behavior can be debugged more simply than in the RTL model. The design is obvious, the code is readable and the function is easily ascertained. Note that there is no explicit controller, as the synthesis mechanism will define the appropriate mechanism. Also notice that the model is defined with a single module. The synthesis mechanism will partition the design depending on the optimization constraints specified. This is easily parameterized, modified and clear.
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
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Manufacturer:Xilinx
Product Categories: FPGAs
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Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
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Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
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