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The first task is to define the types for the VHDL for the entity of the model and this is shown in the following code. Notice that we have defined a new type, sig8, that is a signed type and a vector based on this for the cross product multiplications.
1 library ieee;
2 use ieee.std_logic_1164.all;
Figure 17.1 Cross product multiplier specification.
Figure 17.2 Cross product multiplier data path model.
3 use ieee.numeric_std.all;
4 package cross_product_types is
5 subtype sig8 is signed (7 downto 0);
6 type sig8_vector is array
7 (natural range<>) of sig8;
8 end package;
The entity can now be put together and is shown as follows. Notice that for RTL we require both a clock and a reset.
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use work.cross_product_types.all;
5
6 entity cross_product is
7 port(
8 a,b : in sig8_vector(0 to 7);
9 clk, reset : in bit;
10 result : out signed(15 downto 0)
11 );
12 end entity cross_product;
The basic architecture can be set up with the basic internal signals defined, and the processes
1 architecture rtl of cross_product is
2 signal I : unsigned ( 2 downto 0);
3 signal ai, bi : sig8;
4 signal product, add_in, sum, accumulator : signed (15 downto 0);
5 begin
6 control: process (clk)
7 begin
8 if clkevent and clk = 1 then
9 if reset = 1 then
10 i <= (others => 0);
11 else
12 i <= i + 1;
13 end if;
14 end if;
15 end process;
16 a_mux: ai <= a(i);
17 b_mux <= bi <= b(i);
18 multiply: product <=ai ∗ bi;
19 z_mux: add_in <= X 000 when i = 0 else accumulator;
20
21 accumulate: process (clk)
22 begin
23 if clkevent and clk = 1 then
24 accumulator <= sum;
25 end if;
26 end process;
27
28 output : result <= accumulator;
29 end;
will be explained separately.
Notice that there are two processes, one for the accumulation and the other to handle the multiplication. One important aspect is that it is not immediately obvious what is going on. Even in this simple model it is difficult to extract the key behavior of the state machine. In a complex controller it verges on the impossible unless the structure is well known and understood, which is an important lesson when using any kind of synthesis tool using VHDL or Verilog at any level.
Now reconsider using behavioral VHDL instead. The model uses the same packages and libraries as the RTL model; however, notice that there is no need for an explicit clock or reset.
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use work.cross_product_types.all;
5
6 entity cross_product is
7 port(
8 a,b : in sig8_vector(0 to 7);
9 result : out signed(15 downto 0)
10 );
11 end entity cross_product;
In this model, the architecture becomes much simpler and can be modeled in a much more direct way than the RTL approach.
1 architecture behav of cross_product is
2 begin
3
4 process
5 variable sum : signed(15 downto 0);
6 begin
7 sum := to_signed(0,16);
8 for i in 0 to 7 loop
9 sum := sum + a(i) ∗ b(i);
10 end loop;
11 result <= sum;
12 wait for 100 ns;
13 end process;
14
15 end architecture;
Notice that it is much easier to observe the functionality of the model and also the behavior can be debugged more simply than in the RTL model. The design is obvious, the code is readable and the function is easily ascertained. Note that there is no explicit controller; the synthesis mechanism will define the appropriate mechanism. Also notice that the model is defined with a single process. The synthesis mechanism will partition the design depending on the optimization constraints specified.
Note the wait statement. This introduces an implicit clock delay into the system. Obviously this will depend on the clock mechanism used in reality. There is also an implied reset. If an explicit clock is required then use a wait until rising_edge(clk) or similar approach, while retaining the behavioral nature of the model.
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