TABLE OF CONTENTS

• Preface
• Introduction
  • Verilog vs. VHDL
  • Why FPGAs?
  • Summary
• An FPGA Primer
  • FPGA Evolution
  • Programmable Logic Devices
  • Field Programmable Gate Arrays
  • FPGA Design Techniques
  • Design Constraints using FPGAs
  • Development Kits and Boards
  • Summary
• A VHDL Primer: The Essentials
  • Entity: Model Interface
  • Architecture: Model Behavior
  • Process: Basic Functional Unit in VHDL
  • Basic Variable Types and Operators
  • Decisions and Loops
  • Hierarchical Design
  • Debugging Models
  • Basic Data Types
  • Summary
• A Verilog Primer: The Essentials
  • Modules
  • Connections
  • Wires and Registers
  • Defining the Module Behavior
  • Parameters
  • Variables
  • Data Types
  • Decision Making
  • Loops
  • Summary
• Design Automation of FPGAs
  • Simulation
  • Libraries
  • std_logic Type Definition
  • Synthesis
  • RTL Design Flow
  • Physical Design Flow
  • Place and Route
  • Timing Analysis
  • Design Pitfalls
  • Summary
• Synthesis
  • Numeric Types
  • Wait Statements
  • Assertions
  • Loops
  • Some Interesting Cases Where Synthesis May Fail
  • What Is Being Synthesized?
  • Summary
• High Speed Video Application
  • Introduction
  • The Camera Link Interface
  • Getting Started
  • Specifying the Interfaces
  • Defining the Top Level Design
  • System Block Definitions and Interfaces
  • The Camera Link Interface
  • The PC Interface
  • Summary
• Simple Embedded Processors
  • A Simple Embedded Processor
  • A Simple Embedded Processor Implemented in VHDL
  • A Simple Embedded Processor Implemented in Verilog
  • Soft Core Processors on an FPGA
  • Summary
• Digital Filters
  • Converting S Domain to Z Domain
  • Implementing Z Domain Functions in VHDL
  • Basic Low Pass Filter Model
  • Implementing Z Domain Functions in Verilog
  • Finite Impulse Response Filters
  • Infinite Impulse Response Filters
  • Summary
• Secure Systems
  • Feistel Lattice Structures
  • The Data Encryption Standard (DES)
  • Advanced Encryption Standard
  • Summary
• Memory
  • Modeling Memory in HDLs
  • Read Only Memory
  • Random Access Memory
  • Synchronous RAM
  • Flash Memory
  • Summary
• PS/2 Mouse Interface
  • PS/2 Mouse Basics
  • PS/2 Mouse Commands
  • PS/2 Mouse Data Packets
  • PS/2 Operation Modes
  • PS/2 Mouse with Wheel
  • Basic PS/2 Mouse Handler VHDL
  • Modified PS/2 Mouse Handler VHDL
  • Basic PS/2 Mouse Handler in Verilog
  • Summary
• PS/2 Keyboard Interface
  • PS/2 Keyboard Basics
  • PS/2 Keyboard Commands
  • PS/2 Keyboard Data Packets
  • PS/2 Keyboard Operation Modes
  • Summary
• A Simple VGA Interface
  • Basic Pixel Timing
  • Image Handling
  • A VGA Interface in VHDL
  • A VGA Interface in Verilog
  • Summary
• Serial Communications
  • Manchester Encoding and Decoding
  • Implementing the Manchester Encoding Scheme using VHDL
  • Implementing the Manchester Encoding Scheme using Verilog
  • Serial Communications
  • NRZI (Non-Return-to-Zero-Inverted) Coding and Decoding
  • RS-232
  • Universal Serial Bus
  • Summary
• Design Optimization
  • Design Optimization
  • Techniques for Logic Optimization
  • Improving Performance
  • Summary
• Behavioral Modeling in using HDLs
  • How to Go from RTL to Behavioral HDL Descriptions
  • Implementing the Behavioral Model using VHDL
  • Implementing the Behavioral Model using Verilog
  • Summary
• Mixed Signal Modeling
  • Basic Modeling Approach for VHDL-AMS
  • Introduction to VHDL-AMS
  • VHDL-AMS Analog Pins: TERMINALS
  • Mixed Domain Modeling
  • VHDL-AMS Analog Variables: Quantities
  • Simultaneous Equations in VHDL-AMS
  • A VHDL-AMS Example: A DC Voltage Source
  • A VHDL-AMS Example: Resistor
  • Differential Equations in VHDL-AMS
  • Mixed-Signal Modeling with VHDL-AMS
  • A Basic Switch Model
  • Basic VHDL-AMS Comparator Model
  • Multiple Domain Modeling
  • Introduction to Verilog-AMS
  • Verilog-AMS: Analog ports
  • Mixed Domain Modeling in Verilog-AMS
  • Verilog-AMS Analog Variables
  • Verilog-AMS Analog Equations
  • A Verilog-AMS Example
  • Differential Equations in Verilog-AMS
  • Mixed Signal Modeling with Verilog-AMS
  • Multiple Domain Modeling using Verilog-AMS
  • Summary
• Design Optimization Example: DES
  • The Data Encryption Standard
  • MOODS
  • Initial Design
  • Initial Synthesis
  • Optimizing the Datapath
  • Final Optimization
  • Results
  • Triple DES
  • Comparing the Approaches
  • Summary
• Latches, Flip-Flops, and Registers
  • Latches
  • Flip-Flops
  • Registers
  • Summary
• ALU Functions
  • Logic Functions in VHDL
  • Structural n-Bit Addition
  • Logic Functions in Verilog
  • Configurable n-Bit Addition
  • Two’s Complement
  • Summary
• Finite State Machines in VHDL and Verilog
  • State Transition Diagrams
  • Implementing Finite State Machines in VHDL
  • Implementing Finite State Machines in Verilog
  • Testing the Finite State Machine Model
  • Summary
• Fixed Point Arithmetic
  • Basic Fixed Point Types in VHDL
  • Fixed Point Functions in VHDL
  • Testing the VHDL Fixed Point Functions
  • Fixed Point Types in Verilog
  • Floating Point Types in Verilog
  • Summary
• Counters
  • Basic Binary Counter using VHDL
  • Simple Binary Counter using Verilog
  • Synthesized Simple Binary Counter
  • Shift Register
  • The Johnson Counter
  • BCD Counter
  • Summary
• Decoders and Multiplexers
  • Multiplexers
  • Summary
• Multiplication
  • Basic Binary Multiplication
  • VHDL Unsigned Multiplier
  • Synthesis of the Multiplication Function
  • Simple Multiplication using VHDL
  • Simple Multiplication using Verilog
  • Summary
• Simple 7-Segment (LCD) Displays
  • VHDL LCD Module Decoder
  • Verilog LCD Module Decoder
  • Summary
• Bibliography