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The simplest form of the Verilog handler could use the keyboard clock signal as the system clock and then monitor the data coming from the keyboard. This is shown here:
1 module psmouse (
2 clk, / clock input
3 data / data input
4 );
5
6 input clk;
7 input data;
8
9 wire clk;
10 wire data;
11
12 reg [4:0] index = 5’b10111;
13 reg [23:0] d;
14 reg [7:0] byte1;
15 reg [7:0] byte2;
16 reg [7:0] byte3;
17
18 always @ (negedge clk)
19 begin : count
20 d[index] <= data;
21 if (index > 0) begin
22 index <= index − 1;
23 end
24 else begin
25 index <= 23;
26 byte1 <= d[23:16];
27 byte2 <= d[15:8];
28 byte3 <= d[7:0]
29 end
30 end
31
32 endmodule
This Verilog is very simple: on each falling edge of the clock the current value of the data is read into the next element of the data array (d) and when the complete 24-bits packet has been read in (and index has counted down to zero) then the three bytes are transcribed from the packet.
A modified handler could also be implemented in Verilog, either using the same approach as described for the VHDL model, but also the approach could be taken to simply divide down the clock from a higher frequency reference.
Manufacturer:Xilinx
Product Categories: Special equipment devices and IC
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
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