FONT SIZE : AAA
The trouble with the previous mouse handler is that, although syntactically correct, there could be noise on the mouse clock and data signals leading to an incorrect clocking of the data and so another approach would be to have a much higher frequency signal clock and to monitor the PS/2 clock as if it were a signal. An extra check would be to filter the PS/2 clock so that only if there were a certain number of values the same would the clock be considered to have changed.
1 library ieee;
2 use ieee.std_logic_1164.all;
3
4 entity psmouse is
5 port (
6 clk : in std_logic;
7 ps2_clock : in std_logic;
8 data : in std_logic
9 );
10 end entity psmouse;
11
12 architecture basic of psmouse is
13 signal clk_internal : std_logic := 0 ;
14 signal d : std_logic_vector (23 downto 0);
15 signal byte1 : std_logic_vector (7 downto 0);
16 signal byte2 : std_logic_vector (7 downto 0);
17 signal byte3 : std_logic_vector (7 downto 0);
18 signal index : integer := 23;
19 begin
20 process(clock) is
21 high : integer := 0;
22 low : integer := 0;
23 begin
24 if rising_edge(clock) then
25 if (ps2_clock = 1 ) then
26 if high=8 then
27 clk_internal <= 1 ;
28 high <= 0;
29 low <= 0
30 else
31 high <= high +1;
32 end if;
33 else
34 if low=8 then
35 clk_internal <= 0 ;
36 low <= 0;
37 high <= 0;
38 else
39 low <= low +1;
40 end if;
41 end if;
42 end if;
43 end process;
44 process(clk_internal) is
45 begin
46 if falling_edge(clk_internal) then
47 d(index) <= data;
48 if index>0 then
49 index <= index−1;
50 else
51 byte1 <= d(23 downto 16);
52 byte2 <= d(15 downto 8);
53 byte3 <= d(7 downto 0);
54 index<=23;
55 end if;
56 end if;
57 end process;
58 end architecture basic;
In this case the modified mouse handler waits for eight consecutive highs or lows on the clock signal at the higher internal clock rate of the FPGA and then it will set the internal clock high or low, respectively. Then the same mouse handler routine takes over to manage the data input, this time using the internally generated clock.
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
Support
